参数资料
型号: IDT82V3280DQG
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 通信及网络
英文描述: WAN PLL
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP100
封装: GREEN, TQFP-100
文件页数: 61/167页
文件大小: 1039K
代理商: IDT82V3280DQG
IDT82V3280
WAN PLL
Programming Information
61
June 19, 2006
1F
IN11_CNFG - Input Clock 11 Configu-
ration
IN12_CNFG - Input Clock 12 Configu-
ration
IN13_CNFG - Input Clock 13 Configu-
ration
IN14_CNFG - Input Clock 14 Configu-
ration
PRE_DIV_CH_CNFG - DivN Divider
Channel Selection
PRE_DIVN[7:0]_CNFG - DivN Divider
Division Factor Configuration 1
PRE_DIVN[14:8]_CNFG
Divider Division Factor Configuration 2
IN1_IN2_SEL_PRIORITY_CNFG
Input Clock 1 & 2 Priority Configuration
*
IN3_IN4_SEL_PRIORITY_CNFG
Input Clock 3 & 4 Priority Configuration
*
IN5_IN6_SEL_PRIORITY_CNFG
Input Clock 5 & 6 Priority Configuration
*
IN7_IN8_SEL_PRIORITY_CNFG
Input Clock 7 & 8 Priority Configuration
*
IN9_IN10_SEL_PRIORITY_CNFG
Input Clock 9 & 10 Priority Configura-
tion *
IN11_IN12_SEL_PRIORITY_CNFG -
Input Clock 11 & 12 Priority Configura-
tion *
IN13_IN14_SEL_PRIORITY_CNFG -
Input Clock 13 & 14 Priority Configura-
tion *
DIRECT_D
IV
DIRECT_D
IV
DIRECT_D
IV
DIRECT_D
IV
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
P 89
20
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
P 90
21
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
P 91
22
LOCK_8K
BUCKET_SEL[1:0]
IN_FREQ[3:0]
P 92
23
-
-
-
-
PRE_DIV_CH_VALUE[3:0]
P 93
24
PRE_DIVN_VALUE[7:0]
P 93
25
-
DivN
-
PRE_DIVN_VALUE[14:8]
P 94
26
-
IN2_SEL_PRIORITY[3:0]
IN1_SEL_PRIORITY[3:0]
P 95
27
-
IN4_SEL_PRIORITY[3:0]
IN3_SEL_PRIORITY[3:0]
P 96
28
-
IN6_SEL_PRIORITY[3:0]
IN5_SEL_PRIORITY[3:0]
P 97
29
-
IN8_SEL_PRIORITY[3:0]
IN7_SEL_PRIORITY[3:0]
P 98
2A
-
IN10_SEL_PRIORITY[3:0]
IN9_SEL_PRIORITY[3:0]
P 99
2B
IN12_SEL_PRIORITY[3:0]
IN11_SEL_PRIORITY[3:0]
P 100
2C
IN14_SEL_PRIORITY[3:0]
IN13_SEL_PRIORITY[3:0]
P 101
Input Clock Quality Monitoring Configuration & Status Registers
2E
FREQ_MON_FACTOR_CNFG - Fac-
tor of Frequency Monitor Configuration
ALL_FREQ_MON_THRESHOLD_CN
FG - Frequency Monitor Threshold for
All Input Clocks Configuration
UPPER_THRESHOLD_0_CNFG
Upper Threshold for Leaky Bucket
Configuration 0
LOWER_THRESHOLD_0_CNFG
Lower Threshold for Leaky Bucket
Configuration 0
BUCKET_SIZE_0_CNFG - Bucket
Size for Leaky Bucket Configuration 0
DECAY_RATE_0_CNFG - Decay Rate
for Leaky Bucket Configuration 0
-
-
-
-
FREQ_MON_FACTOR[3:0]
P 102
2F
-
-
-
-
ALL_FREQ_HARD_THRESHOLD[3:0]
P 102
31
-
UPPER_THRESHOLD_0_DATA[7:0]
P 103
32
-
LOWER_THRESHOLD_0_DATA[7:0]
P 103
33
BUCKET_SIZE_0_DATA[7:0]
P 103
34
-
-
-
-
-
-
DECAY_RATE_0_DATA
[1:0]
P 104
Table 42: Register List and Map (Continued)
Address
(Hex)
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reference
Page
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