参数资料
型号: IDT82V3280DQG
厂商: INTEGRATED DEVICE TECHNOLOGY INC
元件分类: 通信及网络
英文描述: WAN PLL
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP100
封装: GREEN, TQFP-100
文件页数: 82/167页
文件大小: 1039K
代理商: IDT82V3280DQG
IDT82V3280
WAN PLL
Programming Information
82
June 19, 2006
IN5_IN6_HF_DIV_CNFG - Input Clock 5 & 6 High Frequency Divider Configuration
Address: 18H
Type: Read / Write
Default Value: 00XXXX00
Bit
Name
Description
7 - 6
IN6_DIV[1:0]
These bits determine whether the HF Divider is used and what the division factor is for IN6 frequency division:
00: Bypassed. (default)
01: Divided by 4.
10: Divided by 5.
11: Reserved.
Reserved.
These bits determine whether the HF Divider is used and what the division factor is for IN5 frequency division:
00: Bypassed. (default)
01: Divided by 4.
10: Divided by 5.
11: Reserved.
5 - 2
-
1 - 0
IN5_DIV[1:0]
7
6
5
4
3
2
1
0
IN6_DIV1
IN6_DIV0
-
-
-
-
IN5_DIV1
IN5_DIV0
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