参数资料
型号: IDT82V3358EDG
厂商: IDT, Integrated Device Technology Inc
文件页数: 2/139页
文件大小: 0K
描述: IC PLL WAN SYNC ETHERNET 64TQFP
标准包装: 160
类型: 时钟/频率发生器,多路复用器
PLL:
主要目的: 以太网,SONET/SDH,Stratum
输入: CMOS,LVDS,PECL
输出: CMOS,LVDS,PECL
电路数: 1
比率 - 输入:输出: 2:4
差分 - 输入:输出: 是/是
频率 - 最大: 622.08MHz
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-TQFP 裸露焊盘
供应商设备封装: 64-TQFP-EP(10x10)
包装: 托盘
IDT82V3358
SYNCHRONOUS ETHERNET WAN PLL
Description
10
May 19, 2009
DESCRIPTION
The IDT82V3358 is an integrated, single-chip solution for the Syn-
chronous Equipment Timing Source for Stratum 3, SMC, 4E and 4
clocks in SONET / SDH equipments, DWDM and Wireless base station,
such as GSM, 3G, DSL concentrator, Router and Access Network appli-
cations.
The device supports three types of input clock sources: recovered
clock from STM-N or OC-n, PDH network synchronization timing and
external synchronization reference timing.
Based on ITU-T G.783 and Telcordia GR-253-CORE, the device con-
sists of T0 and T4 paths. The T0 path is a high quality and highly config-
urable path to provide system clock for node timing synchronization
within a SONET / SDH network. The T4 path is simpler and less config-
urable for equipment synchronization. The T4 path locks independently
from the T0 path or locks to the T0 path.
An input clock is automatically or manually selected for T0 and T4
each for DPLL locking. Both the T0 and T4 paths support three primary
operating modes: Free-Run, Locked and Holdover. In Free-Run mode,
the DPLL refers to the master clock. In Locked mode, the DPLL locks to
the selected input clock. In Holdover mode, the DPLL resorts to the fre-
quency data acquired in Locked mode. Whatever the operating mode is,
the DPLL gives a stable performance without being affected by operat-
ing conditions or silicon process variations.
If the DPLL outputs are processed by T0/T4 APLL, the outputs of the
device will be in a better jitter/wander performance.
The device provides programmable DPLL bandwidths: 0.1 Hz to 560
Hz in 11 steps and damping factors: 1.2 to 20 in 5 steps. Different set-
tings cover all SONET / SDH clock synchronization requirements.
A high stable input is required for the master clock in different appli-
cations. The master clock is used as a reference clock for all the internal
circuits in the device. It can be calibrated within ±741 ppm.
All the read/write registers are accessed through a serial micropro-
cessor interface. The device supports Serial microprocessor interface
mode only.
The device can be used typically in Chapter 3.17 Line Card Applica-
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