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型号： IDT82V3358EDG
厂商： IDT, Integrated Device Technology Inc
文件页数： 65/139页
文件大小： 0K
描述： IC PLL WAN SYNC ETHERNET 64TQFP
标准包装： 160
类型： 时钟/频率发生器，多路复用器
PLL： 是
主要目的： 以太网，SONET/SDH，Stratum
输入： CMOS，LVDS，PECL
输出： CMOS，LVDS，PECL
电路数： 1
比率 - 输入:输出： 2:4
差分 - 输入:输出： 是/是
频率 - 最大： 622.08MHz
电源电压： 3 V ~ 3.6 V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 64-TQFP 裸露焊盘
供应商设备封装： 64-TQFP-EP（10x10）
包装： 托盘
IDT82V3358
SYNCHRONOUS ETHERNET WAN PLL
Functional Description
31
May 19, 2009
3.10
T0 / T4 DPLL OPERATING MODE
The T0/T4 DPLL gives a stable performance in different applications
without being affected by operating conditions or silicon process varia-
tions. It integrates a PFD (Phase & Frequency Detector), a LPF (Low
Pass Filter) and a DCO (Digital Controlled Oscillator), which forms a
closed loop. If no input clock is selected, the loop is not closed, and the
PFD and LPF do not function.
The PFD detects the phase error, including the fast loss, coarse
phase loss and fine phase loss (refer to Chapter 3.7.1.1 Fast Loss to
Chapter 3.7.1.3 Fine Phase Loss). The averaged phase error of the T0/
T4 DPLL feedback with respect to the selected input clock is indicated
by the CURRENT_PH_DATA[15:0] bits. It can be calculated as follows:
Averaged Phase Error (ns) = CURRENT_PH_DATA[15:0] X 0.61
The LPF filters jitters. Its 3 dB bandwidth and damping factor are pro-
grammable. A range of bandwidths and damping factors can be set to
meet different application requirements. Generally, the lower the damp-
ing factor is, the longer the locking time is and the more the gain is.
The DCO controls the DPLL output. The frequency of the DPLL out-
put is always multiplied on the basis of the master clock. The phase and
frequency offset of the DPLL output may be locked to those of the
selected input clock. The current frequency offset with respect to the
master clock is indicated by the CURRENT_DPLL_FREQ[23:0] bits, and
can be calculated as follows:
Current Frequency Offset (ppm) = CURRENT_DPLL_FREQ[23:0] X
0.000011
3.10.1
T0 DPLL OPERATING MODE
The T0 DPLL loop is closed except in Free-Run mode and Holdover
mode.
For a closed loop, different bandwidths and damping factors can be
used depending on DPLL locking stages: starting, acquisition and
locked.
In the first two seconds when the T0 DPLL attempts to lock to the
selected input clock, the starting bandwidth and damping factor are
used. They are set by the T0_DPLL_START_BW[4:0] bits and the
T0_DPLL_START_DAMPING[2:0] bits respectively.
During the acquisition, the acquisition bandwidth and damping factor
are used. They are set by the T0_DPLL_ACQ_BW[4:0] bits and the
T0_DPLL_ACQ_DAMPING[2:0] bits respectively.
When the T0 selected input clock is locked, the locked bandwidth
and damping
factor are
used. They
are
set
by
the
T0_DPLL_LOCKED_BW[4:0]
bits
and
the
T0_DPLL_LOCKED_DAMPING[2:0] bits respectively.
The corresponding bandwidth and damping factor are used when the
T0 DPLL operates in different DPLL locking stages: starting, acquisition
and locked, as controlled by the device automatically.
Only the locked bandwidth and damping factor can be used regard-
less of the T0 DPLL locking stage, as controlled by the AUTO_BW_SEL
bit.
3.10.1.1
Free-Run Mode
In Free-Run mode, the T0 DPLL output refers to the master clock
and is not affected by any input clock. The accuracy of the T0 DPLL out-
put is equal to that of the master clock.
3.10.1.2
Pre-Locked Mode
In Pre-Locked mode, the T0 DPLL output attempts to track the
selected input clock.
The Pre-Locked mode is a secondary, temporary mode.
3.10.1.3
Locked Mode
In Locked mode, the T0 selected input clock is locked. The phase
and frequency offset of the T0 DPLL output track those of the T0
selected input clock.
In this mode, if the T0 selected input clock is in fast loss status and
the FAST_LOS_SW bit is ‘1’, the T0 DPLL is unlocked (refer to
Chapter 3.7.1.1 Fast Loss) and will enter Lost-Phase mode when the
operating mode is switched automatically; if the T0 selected input clock
is in fast loss status and the FAST_LOS_SW bit is ‘0’, the T0 DPLL lock-
ing status is not affected and the T0 DPLL will enter Temp-Holdover
mode automatically.
3.10.1.3.1 Temp-Holdover Mode
The T0 DPLL will automatically enter Temp-Holdover mode with a
selected input clock switch or no qualified input clock available when the
operating mode switch is under external control.
In Temp-Holdover mode, the T0 DPLL has temporarily lost the
selected input clock. The T0 DPLL operation in Temp-Holdover mode
and that in Holdover mode are alike (refer to Chapter 3.10.1.5 Holdover
Mode) except the frequency offset acquiring methods. See
Chapter 3.10.1.5 Holdover Mode for details about the methods. The
method is selected by the TEMP_HOLDOVER_MODE[1:0] bits, as
shown in Table 19:
The device automatically controls the T0 DPLL to exit from Temp-
Holdover mode.
3.10.1.4
Lost-Phase Mode
In Lost-Phase mode, the T0 DPLL output attempts to track the
selected input clock.
The Lost-Phase mode is a secondary, temporary mode.
3.10.1.5
Holdover Mode
In Holdover mode, the T0 DPLL resorts to the stored frequency data
acquired in Locked mode to control its output. The T0 DPLL output is not
Table 19: Frequency Offset Control in Temp-Holdover Mode
TEMP_HOLDOVER_MODE[1:0]
Frequency Offset Acquiring Method
00
the same as that used in Holdover mode
01
Automatic Instantaneous
10
Automatic Fast Averaged
11
Automatic Slow Averaged
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