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参数资料
| 型号： | ISL12022MIBZ-EVAL |
| 厂商： | Intersil |
| 文件页数： | 8/31页 |
| 文件大小： | 0K |
| 描述： | EVAL BOARD FOR ISL12022MIBZ |
| 应用说明： | Addressing Power Issues in Real Time Clock Appls |
| 产品培训模块： | Solutions for Industrial Control Applications |
| 标准包装： | 1 |
| 系列： | * |
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ISL12022M
16
FN6668.9
June 20, 2012
INTERRUPT/ALARM MODE BIT (IM)
This bit enables/disables the interrupt mode of the alarm
function. When the IM bit is set to “1”, the alarm will operate in
the interrupt mode, where an active low pulse width of 250ms
will appear at the IRQ/FOUT pin when the RTC is triggered by the
alarm, as defined by the alarm registers (0Ch to 11h). When the
IM bit is cleared to “0”, the alarm will operate in standard mode,
where the IRQ/FOUT pin will be set low until the ALM status bit is
cleared to “0”.
FREQUENCY OUTPUT AND INTERRUPT BIT (FOBATB)
This bit enables/disables the IRQ/FOUT pin during battery
backup mode (i.e., VBAT power source active). When the FOBATB
is set to “1”, the IRQ/FOUT pin is disabled during battery backup
mode. This means that both the frequency output and alarm
output functions are disabled. When the FOBATB is cleared to
“0”, the IRQ/FOUT pin is enabled during battery backup mode.
Note that the open drain IRQ/FOUT pin will need a pull-up to the
battery voltage to operate in battery backup mode.
FREQUENCY OUT CONTROL BITS (FO <3:0>)
These bits enable/disable the frequency output function and
frequency selection. Default for the ISL12022M is
FO<3:0> = 1h, or 32.768kHz output (FOUT is ON). When the
frequency mode is enabled, it will override the alarm mode at the
IRQ/FOUT pin.
Power Supply Control Register (PWR_VDD)
CLEAR TIME STAMP BIT (CLRTS)
This bit clears Time Stamp VDD to Battery (TSV2B) and Time
Stamp Battery to VDD Registers (TSB2V). The default setting is 0
(CLRTS = 0) and the Enabled setting is 1 (CLRTS = 1).
VDD BROWNOUT TRIP VOLTAGE BITS (VDDTRIP<2:0>)
These bits set the trip level for the VDD alarm, indicating that VDD
has dropped below a preset level. In this event, the LVDD bit in
the Status Register is set to “1”. See Table 6.
Battery Voltage Trip Voltage Register
(PWR_VBAT)
This register controls the trip points for the two VBAT alarms, with
levels set to approximately 85% and 75% of the nominal battery
level.
RESEAL BIT (RESEALB)
This is the Reseal bit for actively disconnecting the VBAT pin from the
internal circuitry. Setting this bit allows the device to disconnect the
battery and eliminate standby current drain while the device is
unused. Once VDD is powered up, this bit is reset and the VBAT pin is
then connected to the internal circuitry.
The application for this bit involves placing the chip on a board with
a battery and testing the board. Once the board is tested and ready
to ship, it is desirable to disconnect the battery to keep it fresh until
the board or unit is placed into final use. Setting RESEALB = “1”
initiates the battery disconnect, and after VDD power is cycled down
and up again, the RESEAL bit is cleared to “0”.
BATTERY LEVEL MONITOR TRIP BITS (VB85TP <2:0>)
Three bits select the first alarm (85% of Nominal VBAT) level for the
battery voltage monitor. There are total of 7 levels that could be
selected for the first alarm. Any of the of levels could be selected as
the first alarm with no reference as to nominal Battery voltage level.
See Table 8.
TABLE 4.
IM BIT
INTERRUPT/ALARM FREQUENCY
0
Single Time Event Set By Alarm
1
Repetitive/Recurring Time Event Set By Alarm
TABLE 5. FREQUENCY SELECTION OF IRQ/FOUT PIN
FREQUENCY,
FOUT
UNITS
FO3
FO2
FO1
FO0
0
Hz
0
000
32768
Hz
0
001
4096
Hz
0
1
0
1024
Hz
0
011
64
Hz
0
100
32
Hz
0
101
16
Hz
0
110
8
Hz
0
111
4
Hz
1
000
2
Hz
1
001
1
Hz
1
010
1/2
Hz
1
011
1/4
Hz
1
100
1/8
Hz
1
101
1/16
Hz
1
110
1/32
Hz
1
ADDR
7
6
5
4
3
2
1
0
09h
CLRTS
0
VDDTrip2 VDDTrip1 VDDTrip0
TABLE 6. VDD TRIP LEVELS
VDDTrip2
VDDTrip1
VDDTrip0
TRIP VOLTAGE
(V)
00
0
2.295
00
1
2.550
01
0
2.805
01
1
3.060
10
0
4.250
10
1
4.675
TABLE 7.
ADDR 7
6
5
432
10
0Ah D RESEALB VB85Tp2 VB85Tp1 VB85Tp0 VB75Tp2 VB75Tp1 VB75Tp0
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