参数资料
型号: ISL6265CHRTZ
厂商: Intersil
文件页数: 15/27页
文件大小: 0K
描述: IC CTRLR MULTI-OUTPUT 48TQFN
标准包装: 50
应用: 控制器,AMD SVI 兼容移动式 CPU
输入电压: 5 V ~ 24 V
输出数: 3
输出电压: 0.5 V ~ 1.55 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(6x6)
包装: 管件
ISL6265C
Power-On Reset
The ISL6265C requires a +5V input supply tied to VCC and PVCC
to exceed a rising power-on reset (POR) threshold before the
controller has sufficient bias to guarantee proper operation. Once
this threshold is reached or exceeded, the ISL6265C has enough
bias to begin checking RTN1, OFS/VFIXEN, ENABLE, and SVI
inputs. Hysteresis between the rising the falling thresholds
assure the ISL6265C will not inadvertently turn-off unless the
bias voltage drops substantially (see “Electrical Specifications”
on page 12).
Core Configuration
The ISL6265C determines the core channel requirements of the
CPU based on the state of the RTN1 pin prior to ENABLE. If RTN1
is low prior to ENABLE, both VDD0 and VDD1 core planes are
required. The core controllers operate as independent
single-phase regulators. RTN1 is connected to the CPU Core1
negative sense point. For single core CPU designs (uniplane),
RTN1 is tied to a +1.8V or greater supply. Prior to ENABLE, RTN1
is detected as HIGH and the ISL6265C drives the core controllers
as a two-phase multi-phase regulator. Dual purpose motherboard
designs should include resistor options to open the CPU Core1
negative sense and connect the RTN1 pin to a pull-up resistor.
Mode Selection
The OFS/VFIXEN pin selects between the AMD defined VFIX and
SVI modes of operation and enables droop if desired in SVI mode
only. If OFS/VFIXEN is tied to VCC, then SVI mode with no droop
on the core output(s) is selected. Connected to +3.3V, VFIX mode
is active with no droop on the core output(s). SVI mode with
droop is enabled when OFS/VFIXEN is tied to ground through a
resistor sized to set the core voltage positive offset. Further
information is provided in “Offset Resistor Selection” on page 20.
Serial VID Interface
The on-board Serial VID Interface (SVI) circuitry allows the
processor to directly control the Core and Northbridge voltage
reference levels within the ISL6265C. The SVC and SVD states
are decoded according to the PWROK and VFIXEN inputs as
described in the following sections. The ISL6265C uses a
digital-to-analog converter (DAC) to generate a reference voltage
based on the decoded SVI value. See Figure 8 for a simple SVI
interface timing diagram.
1
2
3
4
5
6
7
8
9
10
11
12
VCC
SVC
SVD
ENABLE
PWROK
VDD AND VDDNB
METAL_VID
V_SVI
METAL_VID
V_SVI
VDDPWRGD
(PGOOD)
FIXEN
Interval 1 to 2: ISL6265C waits to POR.
Interval 2 to 3: SVC and SVD are externally set to pre-Metal VID code.
Interval 3 to 4: EN locks core output configuration and pre-Metal VID code. All outputs soft-start to this level.
Interval 4 to 5: PGOOD signal goes HIGH indicating proper operation.
Interval 5 to 6: CPU detects VDDPWRGD high and drives PWROK high to allow ISL6265C to prepare for SVI code.
Interval 6 to 7: SVC and SVD data lines communicate change in VID code.
Interval 7 to 8: ISL6265C responds to VID-ON-THE-FLY code change.
Interval 8 to 9: PWROK is driven low and ISL6265C returns all outputs to pre-PWROK Metal VID level.
Interval 9 to 10: PWROK driven high once again by CPU and ISL6265C prepares for SVI code.
Interval 10 to 11: SVC and SVD data lines communicate new VID code.
Interval 11 to 12: ISL6265C drives outputs to new VID code level.
Post 12 : Enable falls and all internal drivers are tri-stated and PGOOD is driven low.
FIGURE 8. SVI INTERFACE TIMING DIAGRAM: TYPICAL PRE-PWROK METAL VID STARTUP
15
FN6976.2
January 11, 2013
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