参数资料
型号: ISL6265CHRTZ
厂商: Intersil
文件页数: 21/27页
文件大小: 0K
描述: IC CTRLR MULTI-OUTPUT 48TQFN
标准包装: 50
应用: 控制器,AMD SVI 兼容移动式 CPU
输入电压: 5 V ~ 24 V
输出数: 3
输出电压: 0.5 V ~ 1.55 V
工作温度: -10°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(6x6)
包装: 管件
ISL6265C
ISL6265C initiates DE in all three regulators. This transition
allows the controller to achieve the highest possible efficiency
over the entire load range for each output. A smooth transition is
facilitated by the R 3 technology ? , which correctly maintains the
internally synthesized ripple current throughout mode transitions
of each regulator.
Uniplane Core
In uniplane mode, the ISL6265C Core regulator is in 2-phase
multiphase mode. The controller operates with both phases fully
controller uses lower MOSFET r DS(ON) sensing to detect output
current.
CORE OC DETECTION
Core outputs feature an OC monitor which compares a voltage set at
the OCSET pin to the voltage measured across the current sense
capacitor, V C . When the voltage across the current sense capacitor
exceeds the programmed trip level, the comparator signals an OC fault.
Figure 11 shows the basic OC functions within the IC.
active, responding rapidly to transients and delivering the
maximum power to the load. When the processor asserts PSI_L
low under reduced load levels, the ISL6265C sheds one phase to
CURRENT
SENSE
SEE FIGURE 9 FOR
ADDITIONAL DETAIL
V c
eliminate switching losses associated with the idle channel. Even
with the regulator operating in single-phase mode, transient
response capability is maintained.
5x
ISP
ISN
+
_
-
While operating in single-phase DE with PSI_L low, the lower
MOSFET driver switches the lower MOSFET off at the point of zero
inductor current to prevent discharge current from flowing from
the output capacitor bank through the inductor. In DCM,
switching frequency is proportionately reduced, thus greatly
reducing both conduction and switching loss. In DCM, the
switching frequency is defined by Equation 12.
5 x V C(OC) @
OC TRIP CURRENT
OC
+
V OCSET
6
BIAS
CKT
6
R BIAS
10μA
OCSET
1.17V
R BIAS
V OCSET
R OCSET
2 ? L ? I O
F DCM = ------------------- ? -------------------------------------
?
V O ?
V O ? ? 1 – --------- ?
2
F CCM
2
1.33
? V IN ?
(EQ. 12)
ISL6265C
FIGURE 11. OC TRIP CIRCUITRY
V C ( OC )
K = ----------------------------
Where F CCM is equivalent to the Core frequency set by Equation 3.
Fault Monitoring and Protection
The ISL6265C actively monitors Core and Northbridge output
voltages and currents to detect fault conditions. These fault
monitors trigger protective measures to prevent damage to the
processor. One common power good indicator is provided for
linking to external system monitors.
Power-Good Signal
The power-good pin (PGOOD) is an open-drain logic output that
signals if the ISL6265C is not regulating Core and Northbridge
output voltages within the proper levels or output current in one
or more outputs has exceeded the maximum current setpoint.
This pin must be tied to a +3.3V or +5V source through a resistor.
During shutdown and soft-start, PGOOD is pulled low and is
released high only after a successful soft-start has raised Core
and Northbridge output voltages within operating limits. PGOOD
is pulled low when an overvoltage, undervoltage, or overcurrent
(OC) condition is detected on any output or when the controller is
disabled by a POR or forcing enable (EN) low. Once a fault
condition is triggered, the controller acts to protect the processor.
The controller latches off and PGOOD is pulled low. Toggling EN
or VCC initiates a soft-start of all outputs. In the event of an OV,
the controller will not initiate a soft-start by toggling EN, but
requires VCC be lowered below the falling POR threshold to reset.
Overcurrent Protection
Core and Northbridge outputs feature two different methods of
The sense capacitor voltage, V C , will increase as inductor current
rises per Equation 7. When the inductor current rises to the OC
trip level, the voltage across the sense capacitor will reach a
maximum based on the resistor ratio K. This maximum value,
V C(OC) , is gained up by a factor of 5 and compared to the static OC
trip level set by the OCSET pin.
The recommended voltage range for V C,OC is 6mV to 25mV,
which sets the resistor divider ratio K, where I OC is the
user-defined OC trip level (see Equation 13). Typical inductor DCR
values are on the order of 1m ? which result in more than enough
voltage drop to support this V C,OC range.
(EQ. 13)
I OC ? DCR
The resistor divider components also impact time-constant
matching, these components need to meet the parallel
combination requirements of Equation 9.
Based on the selected V C(OC) level, the required OC monitor trip
level is set. The recommended V C(OC) level range will result in an
OC monitor trip level range of 30mV to 125mV based on the
internal gain of 5.
This OC monitor trip level sets the voltage level required at the
OCSET pin to create an OC fault at the user-defined OC trip level.
A resistor divider from the RBIAS pin to ground with the mid-point
connected to OCSET sets the voltage at the pin (see Figure 11).
This voltage is internally divided by 6 and compared with V C(OC) .
Working backwards, the voltage required at the OCSET pin to
achieve this OC trip level ranges from 180mV to 0.750mV as
defined in Equation 14.
current sensing. Core output current sensing is achieved via
inductor DCR or discrete resistor sensing. The Northbridge
21
V OCSET = V C ( OC ) ? 30
(EQ. 14)
FN6976.2
January 11, 2013
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