参数资料
| 型号： | ISL6265CHRTZ |
| 厂商： | Intersil |
| 文件页数： | 20/27页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR MULTI-OUTPUT 48TQFN |
| 标准包装： | 50 |
| 应用： | 控制器，AMD SVI 兼容移动式 CPU |
| 输入电压： | 5 V ~ 24 V |
| 输出数： | 3 |
| 输出电压： | 0.5 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 管件 |
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ISL6265C
Selecting RBIAS For Core Outputs
To properly bias the ISL6265C, a reference current is established
by placing a 117k ? , 1% tolerance resistor from the RBIAS pin to
ground. This will provide a highly accurate, 10μA current source
from which OC reference current is derived.
Care must be taken in layout to place the resistor very close to
the RBIAS pin. A good quality signal ground should be connected
to the opposite end of the R BIAS resistor. Do not connect any
other components to this pin as this would negatively impact
performance. Capacitance on this pin could create instabilities
and is to be avoided.
A resistor divider off this pin is used to set the Core side OC trip
level. Additional direction on how to size is provided in “Fault
divider.
Offset Resistor Selection
If the OFS pin is connected to ground through a resistor, the
ISL6265C operates in SVI mode with droop active. The resistor
between the OFS pin and ground sets the positive Core voltage
offset per Equation 11.
PHASE pin low. The ISL6265C has an integrated boot diode
connected from the PVCC pin to the BOOT pin.
Diode Emulation
The ISL6265C implements forced continuous-conduction-mode
(CCM) at heavy load and diode-emulation-mode (DE) at light load,
to optimize efficiency in the entire load range. The transition is
automatically achieved by detecting the inductor current when
PSI_L is low. If PSI_L is high, the controller disables DE and
forces CCM on both Core and NB regulators.
Positive-going inductor current flows either from the source of
the high-side MOSFET, or into the drain of the low-side MOSFET.
Negative-going inductor current flows into the drain of the low-
side MOSFET. When the low-side MOSFET conducts positive
inductor current, the phase voltage is negative with respect to the
GND and PGND pins. Conversely, when the low-side MOSFET
conducts negative inductor current, the phase voltage is positive
with respect to the GND and PGND pins. The ISL6265C monitors
the phase voltage when the low-side MOSFET is conducting
inductor current to determine the direction of the inductor
current.
When the output load current is less than half the inductor ripple
R OFS = ----------------------------
1.2V ? R FB
V OFS
(EQ. 11)
current, the inductor current goes negative. Sinking the negative
inductor through the low-side MOSFET lowers efficiency by
preventing DCM period stretching and allowing unnecessary
Where V OFS is the user defined output voltage offset. Typically,
V OFS is determined by taking half the total output voltage droop.
The resulting value centers the overall output voltage waveform
around the programmed SVID level. For example, R FB of 1k ? and
a total output droop of 24mV would result in an offset voltage of
12mV and a R OFS of 100k ? .
Internal Driver Operation
The ISL6265C features three internal gate-drivers to support the
Core and Northbridge regulators and to reduce solution size. The
drivers include a diode emulation mode, which helps to improve
light-load efficiency.
MOSFET Gate-Drive Outputs
The ISL6265C has internal gate-drivers for the high-side and low-
side N-Channel MOSFETs. The low-side gate-drivers are optimized
for low duty-cycle applications where the low-side MOSFET
conduction losses are dominant, requiring a low r DS(ON) MOSFET.
The LGATE pull-down resistance is low in order to strongly clamp
the gate of the MOSFET below the V GS(th) at turn-off. The current
transient through the gate at turn-off can be considerable
because the gate charge of a low r DS(ON) MOSFET can be large.
Adaptive shoot-through protection prevents a gate-driver output
from turning on until the opposite gate-driver output has fallen
below approximately 1V.
The high-side gate-driver output voltage is measured across the
UGATE and PHASE pins while the low-side gate-driver output
voltage is measured across the LGATE and PGND pins. The power
for the LGATE gate driver is sourced directly from the PVCC pin.
The power for the UGATE gate-driver is sourced from a “boot”
capacitor connected across the BOOT and PHASE pins. The boot
capacitor is charged from a 5V bias supply through a “boot
diode” each time the low-side MOSFET turns on, pulling the
20
conduction losses. In DE, the ISL6265C Core regulators
automatically enter DCM after the PHASE pin has detected
positive voltage and LGATE was allowed to go high. The NB
regulator enters DCM after the PHASE pin has detected positive
voltage and LGATE was allowed to go high for eight consecutive
PWM switching cycles. The ISL6265C turns off the low-side
MOSFET once the phase voltage turns positive, indicating
negative inductor current. The ISL6265C returns to CCM on the
following cycle after the PHASE pin detects negative voltage,
indicating that the body diode of the low-side MOSFET is
conducting positive inductor current.
Efficiency can be further improved with a reduction of
unnecessary switching losses by reducing the PWM frequency. It
is characteristic of the R 3 architecture for the PWM frequency to
decrease while in diode emulation. The extent of the frequency
reduction is proportional to the reduction of load current. Upon
entering DCM, the PWM frequency makes an initial
step-reduction because of a 33% step-increase of the window
voltage V W .
Power-Savings Mode
The ISL6265C has two operating modes to optimize efficiency
based on the state of the PSI_L input from the AMD SVI control
signal. When this input is low, the controller expects to deliver
low power and enters a power-savings mode to improve
efficiency in this low power state. The controller’s operational
modes are designed to work in conjunction with the AMD SVI
control signal to maintain the optimal system configuration for
all conditions.
Northbridge and Dual Plane Core
While PSI_L is high, the controller operates all three regulators in
forced CCM. If PSI_L is asserted low by the SVI interface, the
FN6976.2
January 11, 2013
相关PDF资料 |
PDF描述 |
|---|---|
| ISL6265HRTZ-T | IC CTLR MULTI-OUTPUT 48-TQFN |
| ISL6266AHRZ | IC CORE CTRLR 2PHASE 48-QFN |
| ISL6267HRZ | IC PWM CTRLR MULTIPHASE 48TQFN |
| ISL6268CAZ | IC REG CTRLR BUCK PWM 16-QSOP |
| ISL6269AIRZ | IC REG CTRLR BUCK PWM 16-QFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6265CHRTZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLRS PHS W/EMBEDDED GATE RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6265CIRTZ | 制造商:Intersil Corporation 功能描述:MULTI-OUTPUT CONTROLLER (SINGLE PHASE) WITH EMBEDDED GATE DR - Rail/Tube |
| ISL6265EVAL1Z | 制造商:Intersil Corporation 功能描述: |
| ISL6265HRTZ | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLRS PHS W/EMBEDDED GATE RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6265HRTZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLRS PHS W/EMBEDDED GATE RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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