参数资料
| 型号： | ISL6265CHRTZ |
| 厂商： | Intersil |
| 文件页数： | 24/27页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR MULTI-OUTPUT 48TQFN |
| 标准包装： | 50 |
| 应用： | 控制器，AMD SVI 兼容移动式 CPU |
| 输入电压： | 5 V ~ 24 V |
| 输出数： | 3 |
| 输出电压： | 0.5 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 管件 |
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ISL6265C
(EQ. 25)
P CON_HS = I LOAD r DS ( ON ) _HS ? D
P SW_HS = ----------------------------------------------------------------- + -------------------------------------------------------------
For the high-side (HS) MOSFET, the its conduction loss is written
as Equation 25:
2
?
For the high-side MOSFET, the switching loss is written as
Equation 26:
V IN ? I VALLEY ? t ON ? f SW V IN ? I PEAK ? t OFF ? f SW
2 2
(EQ. 26)
Where:
- I VALLEY is the difference of the DC component of the inductor
current minus 1/2 of the inductor ripple current
- I PEAK is the sum of the DC component of the inductor current
plus 1/2 of the inductor ripple current
- t ON is the time required to drive the device into saturation
- t OFF is the time required to drive the device into cut-off
Component Placement
There are two sets of critical components in a DC/DC converter;
the power components and the small signal components. The
power components are the most critical because they switch
large amount of energy. The small signal components connect to
sensitive nodes or supply critical bypassing current and signal
coupling.
The power components should be placed first and these include
MOSFETs, input and output capacitors, and the inductor. It is
important to have a symmetrical layout for each power train,
preferably with the controller located equidistant from each
power train. Symmetrical layout allows heat to be dissipated
equally across all power trains. Keeping the distance between
the power train and the control IC short helps keep the gate drive
traces short. These drive signals include the LGATE, UGATE,
PGND, PHASE and BOOT.
Selecting The Bootstrap Capacitor
All three integrated drivers feature an internal bootstrap Schottky
diode. Simply adding an external capacitor across the BOOT and
PHASE pins completes the bootstrap circuit. The bootstrap
function is also designed to prevent the bootstrap capacitor from
overcharging due to the large negative swing at the PHASE node.
This reduces voltage stress on the BOOT and PHASE pins.
The bootstrap capacitor must have a maximum voltage rating
VIAS TO
GROUND
PLANE
INDUCTOR
HIGH-SIDE
MOSFETS
GND
VOUT
PHASE
NODE
VIN
OUTPUT
CAPACITORS
SCHOTTKY
DIODE
LOW-SIDE
MOSFETS
INPUT
CAPACITORS
above PVCC + 4V and its capacitance value is selected per
Equation 27:
FIGURE 14. TYPICAL POWER COMPONENT PLACEMENT
C BOOT ≥ ------------------------
Q g
Δ V BOOT
(EQ. 27)
When placing MOSFETs, try to keep the source of the upper
MOSFETs and the drain of the lower MOSFETs as close as
Where:
- Q g is the total gate charge required to turn on the high-side
MOSFET
- Δ V BOOT , is the maximum allowed voltage decay across the
boot capacitor each time the high-side MOSFET is switched
on
As an example, suppose the high-side MOSFET has a total gate
charge Q g , of 25nC at V GS = 5V, and a Δ V BOOT of 200mV. The
calculated bootstrap capacitance is 0.125μF; for a comfortable
margin, select a capacitor that is double the calculated
capacitance. In this example, 0.22μF will suffice. Use a low
temperature-coefficient ceramic capacitor.
PCB Layout Considerations
Power and Signal Layers Placement on the
PCB
As a general rule, power layers should be close together, either
on the top or bottom of the board, with the weak analog or logic
signal layers on the opposite side of the board. The ground-plane
layer should be adjacent to the signal layer to provide shielding.
The ground plane layer should have an island located under the
IC, the compensation components, and the FSET components.
The island should be connected to the rest of the ground plane
layer at one point.
24
thermally possible (see Figure 14). Input high-frequency
capacitors should be placed close to the drain of the upper
MOSFETs and the source of the lower MOSFETs. Place the output
inductor and output capacitors between the MOSFETs and the
load. High-frequency output decoupling capacitors (ceramic)
should be placed as close as possible to the decoupling target
(microprocessor), making use of the shortest connection paths to
any internal planes. Place the components in such a way that the
area under the IC has less noise traces with high dV/dt and di/dt,
such as gate signals and phase node signals.
Signal Ground and Power Ground
The bottom of the ISL6265C QFN package is the signal ground
(GND) terminal for analog and logic signals of the IC. Connect the
GND pad of the ISL6265C to the island of ground plane under the
top layer using several vias, for a robust thermal and electrical
conduction path. Connect the input capacitors, the output
capacitors, and the source of the lower MOSFETs to the power
ground plane.
Routing and Connection Details
Specific pins (and the trace routing from them), require extra
attention during the layout process. The following sub-sections
outline concerns by pin name.
FN6976.2
January 11, 2013
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6265CHRTZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLRS PHS W/EMBEDDED GATE RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6265CIRTZ | 制造商:Intersil Corporation 功能描述:MULTI-OUTPUT CONTROLLER (SINGLE PHASE) WITH EMBEDDED GATE DR - Rail/Tube |
| ISL6265EVAL1Z | 制造商:Intersil Corporation 功能描述: |
| ISL6265HRTZ | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLRS PHS W/EMBEDDED GATE RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6265HRTZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLRS PHS W/EMBEDDED GATE RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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