参数资料
| 型号： | ISL6265CHRTZ |
| 厂商： | Intersil |
| 文件页数： | 16/27页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR MULTI-OUTPUT 48TQFN |
| 标准包装： | 50 |
| 应用： | 控制器，AMD SVI 兼容移动式 CPU |
| 输入电压： | 5 V ~ 24 V |
| 输出数： | 3 |
| 输出电压： | 0.5 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 管件 |
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ISL6265C
Pre-PWROK Metal VID
Assuming the OFS/VFIXEN pin is not tied to +3.3V during
controller configuration, typical motherboard start-up begins with
the controller decoding the SVC and SVD inputs to determine the
pre-PWROK metal VID setting (see Table 1). Once the enable
input (EN) exceeds the rising enable threshold, the ISL6265C
decodes and locks the decoded value in an on-board hold
register.
The internal DAC circuitry begins to ramp Core and Northbridge
planes to the decoded pre-PWROK metal VID output level. The
digital soft-start circuitry ramps the internal reference to the
target gradually at a fixed rate of approximately 2mV/μs. The
controlled ramp of all output voltage planes reduces in-rush
current during the soft-start interval. At the end of the soft-start
interval, the PGOOD output transitions high indicating all output
planes are within regulation limits.
SVI MODE
Once the controller has successfully soft-started and PGOOD
transitions high, the processor can assert PWROK to signal the
ISL6265C to prepare for SVI commands. The controller actively
monitors the SVI interface for set VID commands to move the
plane voltages to start-up VID values. Details of the SVI Bus
protocol are provided in the AMD Design Guide for Voltage
Regulator Controllers Accepting Serial VID Codes specification.
Once a set VID command is received, the ISL6265C decodes the
information to determine which output plane is affected and the
VID target required (see Table 3).The internal DAC circuitry steps
the required output plane voltage to the new VID level. During
this time, one or more of the planes could be targeted. In the
event either core voltage plane, VDD0 or VDD1, is commanded to
power-off by serial VID commands, the PGOOD signal remains
asserted. The Northbridge voltage plane must remain active
SVC
TABLE 1. PRE-PWROK METAL VID CODES
SVD OUTPUT VOLTAGE (V)
during this time.
If the PWROK input is de-asserted, then the controller steps both
Core and Northbridge planes back to the stored pre-PWROK
0
0
1
1
0
1
0
1
1.1
1.0
0.9
0.8
metal VID level in the holding register from initial soft-start. No
attempt is made to read the SVC and SVD inputs during this time.
If PWROK is reasserted, then the on-board SVI interface waits for
a set VID command.
If EN goes low during normal operation, all internal drivers are
If the EN input falls below the enable falling threshold, the
ISL6265C tri-states all outputs. PGOOD is pulled low with the loss
of EN. The Core and Northbridge planes will decay based on
output capacitance and load leakage resistance. If bias to VCC
falls below the POR level, the ISL6265C responds in the same
manner previously described. Once VCC and EN rise above their
respective rising thresholds, the internal DAC circuitry re-acquires
a pre-PWROK metal VID code and the controller soft-starts.
VFIX MODE
In VFIX Mode, the SVC and SVD levels fixed external to the
controller through jumpers to either GND or VDDIO. These inputs
are not expected to change. In VFIX mode, the IC decodes the
SVC and SVD states per Table 2.
TABLE 2. VFIXEN VID CODES
tri-stated and PGOOD is pulled low. This event clears the
pre-PWROK metal VID code and forces the controller to check
SVC and SVD upon restart.
A POR event on VCC during normal operation will shutdown all
regulators and PGOOD is pulled low. The pre-PWROK metal VID
code is not retained.
VID-On-the-Fly Transition
Once PWROK is high, the ISL6265C detects this flag and begins
monitoring the SVC and SVD pins for SVI instructions. The
microprocessor will follow the protocol outlined in the following
sections to send instructions for VID-on-the-Fly transitions. The
ISL6265C decodes the instruction and acknowledges the new
VID code. For VID codes higher than the current VID level, the
ISL6265C begins stepping the required regulator output(s) to the
new VID target with a typical slew rate of 7.5mV/μs, which meets
SVC
0
0
1
1
SVD
0
1
0
1
OUTPUT VOLTAGE (V)
1.4
1.2
1.0
0.8
the AMD requirements.
When the VID codes are lower than the current VID level, the
ISL6265C begins stepping the regulator output to the new VID
target with a typical slew rate of -7.5mV/μs. Both Core and NB
regulators are always in CCM during a down VID transition. The
AMD requirements under these conditions do not require the
regulator to meet the minimum slew rate specification of
Once enabled, the ISL6265C begins to soft-start both Core and
Northbridge planes to the programmed VFIX level. The internal
soft-start circuitry slowly ramps the reference up to the target
value. The same fixed internal rate of approximately 2mV/μs
results in a controlled ramp of the power planes. Once soft-start
has ended and all output planes are within regulation limits, the
PGOOD pin transitions high.
and PGOOD status.
16
-5mV/μs. In either case, the slew rate is not allowed to exceed
10mV/μs. The ISL6265C does not change the state of PGOOD
(VDDPWRGD in AMD specifications) when a VID-on-the-fly
transition occurs.
SVI WIRE Protocol
The SVI wire protocol is based on the I 2 C bus concept. Two wires
(serial clock (SVC) and serial data (SVD)), carry information
between the AMD processor (master) and VR controller (slave) on
the bus. The master initiates and terminates SVI transactions
FN6976.2
January 11, 2013
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6265CHRTZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLRS PHS W/EMBEDDED GATE RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6265CIRTZ | 制造商:Intersil Corporation 功能描述:MULTI-OUTPUT CONTROLLER (SINGLE PHASE) WITH EMBEDDED GATE DR - Rail/Tube |
| ISL6265EVAL1Z | 制造商:Intersil Corporation 功能描述: |
| ISL6265HRTZ | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLRS PHS W/EMBEDDED GATE RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6265HRTZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLRS PHS W/EMBEDDED GATE RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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