参数资料
| 型号： | ISL6265CHRTZ |
| 厂商： | Intersil |
| 文件页数： | 4/27页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR MULTI-OUTPUT 48TQFN |
| 标准包装： | 50 |
| 应用： | 控制器，AMD SVI 兼容移动式 CPU |
| 输入电压： | 5 V ~ 24 V |
| 输出数： | 3 |
| 输出电压： | 0.5 V ~ 1.55 V |
| 工作温度： | -10°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-WFQFN 裸露焊盘 |
| 供应商设备封装： | 48-TQFN-EP（6x6） |
| 包装： | 管件 |
第1页第2页第3页当前第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页
ISL6265C
Pin Descriptions
PIN(s)
1
2
3
4
5
6
7
8
9, 19
10, 20
11, 21
12, 22
13, 14, 23, 24
15, 16
18, 17
30
31, 29
32, 28
33, 27
34, 26
35, 25
SYMBOL(s)
OFS/VFIXEN
PGOOD
PWROK
SVD
SVC
ENABLE
RBIAS
OCSET
VDIFF0, VDIFF1
FB0, FB1
COMP0, COMP1
VW0, VW1
ISP0, ISN0, ISP1, ISN1
VSEN0, RTN0
VSEN1, RTN1
PVCC
LGATE0, LGATE1
PGND0, PGND1
PHASE0, PHASE1
UGATE0, UGATE1
BOOT0, BOOT1
4
DESCRIPTION
A resistor from this pin to GND programs a DC current source, which generates a positive offset voltage
across the resistor between FB and VDIFF pins. In this case, the OFS pin voltage is +1.2V and VFIX mode
is not enabled. If OFS is pulled up to +3.3V, VFIX mode is enabled, the DAC decodes the SVC and SVD
inputs to determine the programmed voltage, and the OFS function is disabled. If OFS is pulled up to +5V,
the OFS function and VFIX mode are disabled.
Controller power-good open-drain output. This pin is typically pulled up externally by a 2.0k ? resistor to
+3.3V. During normal operation, this pin indicates whether all output voltages are within specified
overvoltage and undervoltage limits and no overcurrent condition is present. If any output voltage
exceeds these limits or a reset event occurs, the pin is pulled low. This pin is always low prior to the end
of soft-start.
System power good input. When this pin is high, the SVI interface is active and I 2 C protocol is running.
While this pin is low, the SVC, SVD, and VFIXEN input states determine the pre-PWROK metal VID or VFIX
mode voltage. This pin must be low prior to the ISL6265C PGOOD output going high per the AMD SVI
Controller Guidelines.
This pin is the serial VID data bidirectional signal to and from the master device on the AMD processor.
This pin is the serial VID clock input from the AMD processor.
Digital input enable. A high level logic signal on this pin enables the ISL6265C.
A 117k ? resistor from RBIAS to GND sets internal reference currents. The addition of capacitance to this
pin must be avoided and can create instabilities in operation.
CORE_0 and CORE_1 common overcurrent protection selection input. The voltage on this pin sets the
(ISPx - ISNx) voltage limit for OC trip.
Output of the CORE_0 and CORE_1 differential amplifiers.
These pins are the output voltage feedback to the inverting input of the CORE_0 and CORE_1 error
amplifiers.
The output of the CORE_0 and CORE_1 controller error amplifiers respectively. FBx, VDIFFx, and COMPx
pins are tied together through external R-C networks to compensate the regulator
A resistor from this pin to corresponding COMPx pin programs the switching frequency (for example,
6.81k ~ 300kHz).
These pins are used for differentially sensing the corresponding channel output current. The sensed
current is used for channel balancing, protection, and core load line regulation.
Connect ISN0 and ISN1 to the node between the RC sense elements surrounding the inductor of their
respective channel. Tie the ISP0 and ISP1 pins to the VCORE side of their corresponding channel’s sense
capacitor. These pins can also be used for discrete resistor sensing.
Inputs to the CORE_0 VR controller precision differential remote sense amplifier. Connect to the sense
pins of the VDD0_FB[H,L] portion of the processor.
Inputs to the CORE_1 VR controller precision differential remote sense amplifier. Connect to the sense
pins of the VDD1_FB[H,L] portion of the processor. The RTN1 pin is also used for detection of the
VDD_PLANE_STRAP signal prior to enable.
The power supply pin for the internal MOSFET gate drivers of the ISL6265C. Connect this pin to a +5V
power supply. Decouple this pin with a quality 1.0μF ceramic capacitor.
Connect these pins to the corresponding lower MOSFET gate(s).
The return path of the lower gate driver for CORE_0 and CORE_1 respectively. Connect these pins to the
corresponding sources of the lower MOSFETs.
Switch node of the CORE_0 and CORE_1 controllers. Connect these pins to the sources of the
corresponding upper MOSFET(s). These pins are the return path for the upper MOSFET drives.
Connect these pins to the corresponding upper MOSFET gate(s). These pins control the upper MOSFET
gate(s) and are monitored for shoot-through prevention.
These pins provide the bias voltage for the corresponding upper MOSFET drives. Connect these pins to
appropriately chosen external bootstrap capacitors. Internal bootstrap diodes connected to the PVCC pin
provide the necessary bootstrap charge.
FN6976.2
January 11, 2013
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6265CHRTZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLRS PHS W/EMBEDDED GATE RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6265CIRTZ | 制造商:Intersil Corporation 功能描述:MULTI-OUTPUT CONTROLLER (SINGLE PHASE) WITH EMBEDDED GATE DR - Rail/Tube |
| ISL6265EVAL1Z | 制造商:Intersil Corporation 功能描述: |
| ISL6265HRTZ | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLRS PHS W/EMBEDDED GATE RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6265HRTZ-T | 功能描述:电流型 PWM 控制器 MULTI-OUTPUT CNTRLRS PHS W/EMBEDDED GATE RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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