参数资料
型号: ISL6306IRZ-T
厂商: Intersil
文件页数: 14/33页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 40-QFN
标准包装: 4,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 275kHz
占空比: 66.7%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL6306
is driven by the position of the error amplifier output signal,
V COMP , minus the current correction signal relative to the
sawtooth ramp as illustrated in Figure 7. When the modified
V COMP voltage crosses the sawtooth ramp, the PWM output
transitions high. The MOSFET driver detects the change in
state of the PWM signal and turns off the synchronous
MOSFET and turns on the upper MOSFET. The PWM signal
will remain high until the pulse termination signal marks the
beginning of the next cycle by triggering the PWM signal low.
INDUCTOR DCR SENSING
An inductor ’s winding is characteristic of a distributed
resistance as measured by the DCR (Direct Current
Resistance) parameter. Consider the inductor DCR as a
separate lumped quantity, as shown in Figure 4. The
channel current (I L ) flowing through the inductor, will also
pass through the DCR. Equation 3 shows the s-domain
equivalent voltage across the inductor V L .
Current Sampling
V L = I L ? ( s ? L + DCR )
(EQ. 3)
During the forced off-time following a PWM transition low,
the associated channel current sense amplifier uses the
I SEN inputs to reproduce a signal proportional to the inductor
current (I L ). This current gets sampled starting
1/6 period after each PWM goes low and continuously gets
A simple RC network across the inductor extracts the DCR
voltage, as shown in Figure 4.
The voltage on the capacitor (V C ) can be shown to be
proportional to the channel current (I L ) see Equation 4.
? s ? ------------- + 1 ? ? ( DCR ? I )
V C = ---------------------------------------------------------------------
sampled for 1/3 period, or until the PWM goes high,
whichever comes first. No matter the current sense method,
the sense current (I SEN ) is simply a scaled version of the
inductor current. Coincident with the falling edge of the PWM
? DCR ? L
L
( s ? RC + 1 )
(EQ. 4)
signal, the sample and hold circuitry samples the sensed
current signal (I SEN ) as illustrated in Figure 3.
Therefore, the sample current (I n ) is proportional to the
output current and held for one switching cycle. The sample
current is used for current balance, load-line regulation, and
If the RC network components are selected such that the RC
time constant (= R*C) matches the inductor time constant
(= L/DCR), the voltage across the capacitor (V C ) is equal to
the voltage drop across the DCR (i.e., proportional to the
channel current).
overcurrent protection.
V IN
IL ( s )
I L
L
DCR
V OUT
ISL6605
INDUCTOR
C OUT
V L
PWM
V C (s)
R
C
I SEN
PWM(n)
ISL6306 INTERNAL CIRCUIT
R ISEN(n)
0.5Tsw
SAMPLE CURRENT, I n
I n
(PTC)
SAMPLE
SWITCHING PERIOD
AND
HOLD
+
ISEN-(n)
I SEN = I ------------------
L R
TIME
FIGURE 3. SAMPLE AND HOLD TIMING
Current Sensing
The ISL6306 supports inductor DCR sensing, MOSFET
r DS(ON) sensing, or resistive sensing techniques. The
internal circuitry, shown in Figures 4, 5, and 6, represents
one channel of an N-channel converter. This circuitry is
repeated for each channel in the converter, but may not be
active depending on the status of the PWM3 and PWM4
pins, as described in “PWM Operation” on page 13.
14
-
ISEN+(n)
DCR
ISEN
FIGURE 4. DCR SENSING CONFIGURATION
With the internal low-offset current amplifier, the capacitor
voltage (V C ) is replicated across the sense resistor (R ISEN ).
Therefore the current out of ISEN+ pin (I SEN ) is proportional
to the inductor current.
FN9226.1
May 5, 2008
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