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参数资料
| 型号： | ISL6306IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 23/33页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 40-QFN |
| 标准包装： | 4,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 275kHz |
| 占空比： | 66.7% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ISL6306
During TD2 and TD4, ISL6306 digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R ss from SS pin to GND. The
second soft-start ramp time TD2 and TD4 can be calculated
based on Equations 15 and 16:
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID code.
When the output voltage at V SEN is below the undervoltage
threshold, VR_RDY is pulled low.
Overvoltage Protection
1.1xR SS
( V VID – 1.1 ) xR SS
TD2 = ------------------------ ( μ s )
6.25x25
TD4 = ------------------------------------------------ ( μ s )
6.25x25
(EQ. 15)
(EQ. 16)
Regardless of the VR being enabled or not, the ISL6306
overvoltage protection (OVP) circuit will be active after its
POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and before
the second soft-start, the OVP threshold is 1.275V. Once the
For example, when VID is set to 1.5V and the Rss is set at
100k Ω , the first soft-start ramp time TD2 will be 704μs and
the second soft-start ramp time TD4 will be 256μs.
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay TD5. The
typical value for TD5 is 85μs.
VOUT, 500mV/DIV
controller detects valid VID input, the OVP trip point will be
changed to VID plus 175mV.
Two actions are taken by the ISL6306 to protect the
microprocessor load when an overvoltage condition occurs.
At the inception of an overvoltage event, all PWM outputs
are commanded low instantly (less than 20ns) until the
voltage at VDIFF falls below 0.4V. This causes the Intersil
drivers to turn on the lower MOSFETs and pull the output
voltage below a level that might cause damage to the load.
The PWM outputs remain low until VDIFF falls below 0.4V,
and then PWM signals enter a high-impedance state. The
Intersil drivers respond to the high-impedance input by
turning off both upper and lower MOSFETs. If the
TD1
TD2
TD3 TD4
TD5
overvoltage condition reoccurs, the ISL6306 will again
command the lower MOSFETs to turn on. The ISL6306 will
EN_VTT
VR_REDY
500μs/DIV
FIGURE 11. SOFT-START WAVEFORMS
Fault Monitoring and Protection
The ISL6306 actively monitors output voltage and current to
continue to protect the load in this fashion as long as the
overvoltage condition occurs.
Once an overvoltage condition is detected, normal PWM
operation ceases until the ISL6306 is reset. Cycling the
voltage on EN_PWR, EN_VTT or VCC below the POR-
falling threshold will reset the controller. Cycling the VID
codes will not reset the controller.
VR_RDY
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to
UV
OC
-
+
100μA
I 1
external system monitors. The schematic in Figure 12
outlines the interaction between the fault monitors and the
50%
DELAY
REPEAT FOR
EACH CHANNEL
VR_RDY signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
DAC
SOFT-START, FAULT
AND CONTROL LOGIC
-
OC
+
100μA
I AVG
that the soft-start period is completed and the output voltage
is within the regulated range. VR_RDY is pulled low during
shutdown and releases high after a successful soft-start and
a fixed delay TD5. VR_RDY will be pulled low when an
V DIFF
+
-
OV
undervoltage or overvoltage condition is detected, or the
controller is disabled by a reset from EN_PWR, EN_VTT,
VID + 0.175V
POR, or VID OFF-code.
FIGURE 12. VR_RDY AND PROTECTION CIRCUITRY
23
FN9226.1
May 5, 2008
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| ISL6307ACRZ | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6307ACRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
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| ISL6307AIRZ-T | 功能描述:IC REG CTRLR BUCK PWM VM 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6307BCRZ | 功能描述:软开关 PWM 控制器 W/ANNEAL 6-PHS VR11 CNTRLR COM RoHS:否 制造商:Fairchild Semiconductor 输出端数量: 输出电流: 开关频率: 工作电源电压:30 V 电源电流: 最大工作温度:+ 105 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 封装:Reel |
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