参数资料
| 型号： | ISL6323CRZ |
| 厂商： | Intersil |
| 文件页数： | 15/36页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM MONO 48-QFN |
| 标准包装： | 43 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页当前第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
ISL6323
(EQ. 9)
I SEN = I L ? ------------------
.
DCR
R ISEN
The effective internal R ISEN resistance is important to the
current sensing process because it sets the gain of the load
line regulation loop when droop is enabled as well as the
gain of the channel-current balance loop and the overcurrent
trip level. The effective internal R ISEN resistance is user
programmable and is set through use of the RSET pin.
Placing a single resistor, R SET , from the RSET pin to the
VCC pin programs the effective internal R ISEN resistance
according to Equation 10.
correction for Channel 1 represented. In the figure, the cycle
average current, I AVG , is compared with the Channel 1
sample, I 1 , to create an error signal I ER .
The filtered error signal modifies the pulse width
commanded by V COMP to correct any unbalance and force
I ER toward zero. The same method for error signal
correction is applied to each active channel.
VID Interface
The ISL6323 supports hybrid power control of AMD
processors which operate from either a 6-bit parallel VID
R ISEN = ---------- ? R SET
3
400
(EQ. 10)
interface (PVI) or a serial VID interface (SVI). The VID1/SEL
pin is used to command the ISL6323 into either the PVI
The North Bridge regulator samples the load current in the
same manner as the Core regulator does. The R SET resistor
will program all the effective internal R ISEN resistors to the
same value.
Channel-Current Balance
One important benefit of multiphase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
mode or the SVI mode. Whenever the EN pin is held LOW,
both the multiphase Core and single-phase North Bridge
Regulators are disabled and the ISL6323 is continuously
sampling voltage on the VID1/SEL pin. When the EN pin is
toggled HIGH, the status of the VID1/SEL pin will latch the
ISL6323 into either PVI or SVI mode. This latching occurs on
the rising edge of the EN signal.If the VID1/SEL pin is held
LOW during the latch, the ISL6323 will be placed into SVI
mode. If the VID1/SEL pin is held HIGH during the latch, the
ISL6323 will be placed into PVI mode. For the ISL6323 to
properly enter into either mode, the level on the VID1/SEL
pin must be stable no less that 1μs prior to the EN signal
transitioning from low to high.
V COMP
+
-
MODULATOR
RAMP
+
-
PWM1
TO GATE
CONTROL
LOGIC
6-Bit Parallel VID Interface (PVI)
With the ISL6323 in PVI mode, the single-phase North
FILTER
f(s)
WAVEFORM
Bridge regulator is disabled. Only the multiphase controller is
active in PVI mode to support uniplane VDD only
I ER
+
-
I AVG
÷ N
Σ
I 4
I 3
I 2
processors. Table 1 shows the 6-bit parallel VID codes and
the corresponding reference voltage.
TABLE 1. 6-BIT PARALLEL VID CODES
VID5 VID4 VID3 VID2 VID1 VID0 VREF
I 1
NOTE: Channel 3 and 4 are optional.
FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT-
BALANCE ADJUSTMENT
In order to realize the thermal advantage, it is important that
each channel in a multiphase converter be controlled to
carry about the same amount of current at any load level. To
achieve this, the currents through each channel must be
sampled every switching cycle. The sampled currents, I n ,
from each active channel are summed together and divided
by the number of active channels. The resulting cycle
average current, I AVG , provides a measure of the total load
current demand on the converter during each switching
cycle. Channel-current balance is achieved by comparing
the sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented current
balance method is illustrated in Figure 6, with error
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
15
FN9278.5
May 17, 2011
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6323CRZR5285 | 制造商:Intersil Corporation 功能描述: |
| ISL6323CRZ-T | 功能描述:IC HYBRID CTRLR PWM MONO 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6323EVAL1Z | 功能描述:EVAL BOARD 1 FOR ISL6323 RoHS:是 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:* 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
| ISL6323IRZ | 功能描述:IC HYBRID CTRLR PWM MONO 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6323IRZ-T | 功能描述:IC HYBRID CTRLR PWM MONO 48-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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