参数资料
型号: ISL6323CRZ
厂商: Intersil
文件页数: 20/36页
文件大小: 0K
描述: IC HYBRID CTRLR PWM MONO 48-QFN
标准包装: 43
应用: 控制器,AMD SVI
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 最高 2V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 管件
ISL6323
V OUT
VSEN
R FB
I DVC = I C
+
V OFS
-
R FB
FB
VREF
+
-
E/A
DVC
C DVC
I DVC
R DVC
FB
C C
I C
R C
COMP
I OFS
+
-
2x
-
+
ERROR
AMPLIFIER
-
VDAC+RGND
ISL6323 INTERNAL CIRCUIT
+
+
-
+
1.6V
FIGURE 11. DYNAMIC VID COMPENSATION NETWORK
R OFS
OFS
GND
ISL6323
-
GND
0.3V
VCC
This VID-on-the-fly compensation network works by
sourcing AC current into the FB node to offset the effects of
the AC current flowing from the FB to the COMP pin during a
VID transition. To create this compensation current the
FIGURE 10. POSITIVE OFFSET OUTPUT VOLTAGE
PROGRAMMING
Dynamic VID
The AMD processor does not step the output voltage
commands up or down to the target voltage, but instead
passes only the target voltage to the ISL6323 through either
the PVI or SVI interface. The ISL6323 manages the resulting
VID-on-the-Fly transition in a controlled manner, supervising
a safe output voltage transition without discontinuity or
disruption. The ISL6323 begins slewing the DAC at
3.25mV/μs until the DAC and target voltage are equal. Thus,
the total time required for a dynamic VID transition is
dependent only on the size of the DAC change.
To further improve dynamic VID performance, ISL6323 also
implements a proprietary DAC smoothing feature. The
external series RC components connected between DVC
ISL6323 sets the voltage on the DVC pin to be 2x the voltage
on the REF pin. Since the error amplifier forces the voltage
on the FB pin and the REF pin to be equal, the resulting
voltage across the series RC between DVC and FB is equal
to the REF pin voltage. The RC compensation components,
R DVC and C DVC , can then be selected to create the desired
amount of compensation current.
The amount of compensation current required is dependant
on the modulator gain of the system, K1, and the error
amplifier RC components, R C and C C , that are in series
between the FB and COMP pins. Use Equations 16, 17, and
18 to calculate the RC component values, R DVC and C DVC ,
for the VID-on-the-fly compensation network. For these
equations: V IN is the input voltage for the power train; V P-P
is the oscillator ramp amplitude (1.5V); and R C and C C are
the error amplifier RC components between the FB and
COMP pins.
V IN
V P – P
A = -----------------
and FB limit any stair-stepping of the output voltage during a
VID-on-the-Fly transition.
K1 = ----------------
K1
K1 – 1
(EQ. 16)
Compensating Dynamic VID Transitions
During a VID transition, the resulting change in voltage on
the FB pin and the COMP pin causes an AC current to flow
through the error amplifier compensation components from
R RCOMP = A × R C
A
C C
C RCOMP = --------
(EQ. 17)
(EQ. 18)
the FB to the COMP pin. This current then flows through the
feedback resistor, R FB , and can cause the output voltage to
overshoot or undershoot at the end of the VID transition. In
order to ensure the smooth transition of the output voltage
during a VID change, a VID-on-the-fly compensation
network is required. This network is composed of a resistor
and capacitor in series, R DVC and C DVC , between the DVC
and the FB pin.
20
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The integrated drivers incorporate a unique adaptive deadtime
control technique to minimize deadtime, resulting in high
efficiency from the reduced freewheeling time of the lower
MOSFET body-diode conduction, and to prevent the upper and
lower MOSFETs from conducting simultaneously. This is
accomplished by ensuring either rising gate turns on its
MOSFET with minimum and sufficient delay after the other has
turned off.
FN9278.5
May 17, 2011
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