参数资料
| 型号： | ISL6324ACRZ |
| 厂商： | Intersil |
| 文件页数： | 20/40页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM DUAL 48QFN |
| 标准包装： | 43 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6324A
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
VSEN
R FB
I DVC = I C
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
I DVC
C C
I C
R C
output voltage under load can effectively be level shifted
C DVC
R DVC
down so that a larger positive spike can be sustained without
DVC
FB
COMP
crossing the upper specification limit.
As shown in Figure 8, with the FS resistor tied to ground, the
-
average current of all active channels, I AVG , flows from FB
through a load-line regulation resistor R FB . The resulting
+
ERROR
AMPLIFIER
voltage drop across R FB is proportional to the output current,
effectively creating an output voltage droop with a
VDAC+RGND
ISL6324A INTERNAL CIRCUIT
steady-state value defined as in Equation 12:
FIGURE 9. DYNAMIC VID COMPENSATION NETWORK
V DROOP = I AVG ? R FB
(EQ. 12)
during a VID change, a VID-on-the-fly compensation
network is required. This network is composed of a resistor
V OUT = V REF – ? ------------- ? DCR ? ? ---------- ? --------------- ? ? K ? R FB ?
R SET ?
? 3
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage as a function of load current is
shown in Equation 13.
? I OUT 400 1 ?
? N ?
(EQ. 13)
In Equation 13, V REF is the reference voltage, I OUT is the
total output current of the converter, K is the DC gain of the
RC filter across the inductor (K is defined in Equation 7), N is
the number of active channels, and DCR is the Inductor
DCR value.
Dynamic VID
The AMD processor does not step the output voltage
commands up or down to the target voltage, but instead
passes only the target voltage to the ISL6324A through
either the PVI or SVI interface. The ISL6324A manages the
resulting VID-on-the-Fly transition in a controlled manner,
supervising a safe output voltage transition without
discontinuity or disruption. The ISL6324A begins slewing the
DAC at 3.25mV/μs until the DAC and target voltage are
equal. Thus, the total time required for a dynamic VID
transition is dependent only on the size of the DAC change.
and capacitor in series, R DVC and C DVC , between the DVC
and the FB pin.
This VID-on-the-fly compensation network works by
sourcing AC current into the FB node to offset the effects of
the AC current flowing from the FB to the COMP pin during a
VID transition. To create this compensation current the
ISL6324A sets the voltage on the DVC pin to be 2x the
voltage on the REF pin. Since the error amplifier forces the
voltage on the FB pin and the REF pin to be equal, the
resulting voltage across the series RC between DVC and FB
is equal to the REF pin voltage. The RC compensation
components, R DVC and C DVC , can then be selected to
create the desired amount of compensation current.
The amount of compensation current required is dependant
on the modulator gain of the system, K1, and the error
amplifier RC components, R C and C C , that are in series
between the FB and COMP pins. Use Equations 14, 15 and
16 to calculate the RC component values, R DVC and C DVC ,
for the VID-on-the-fly compensation network. For these
equations: V IN is the input voltage for the power train; V P-P
is the oscillator ramp amplitude (1.5V); and R C and C C are
the error amplifier RC components between the FB and
COMP pins.
A = -----------------
V IN
C RCOMP = --------
To further improve dynamic VID performance, ISL6324A
also implements a proprietary DAC smoothing feature. The
external series RC components connected between DVC
and FB limit any stair-stepping of the output voltage during a
VID-on-the-Fly transition.
Compensating Dynamic VID Transitions
During a VID transition, the resulting change in voltage on
the FB pin and the COMP pin causes an AC current to flow
K1
K1 – 1
K1 = ----------------
V P – P
R RCOMP = A × R C
C C
A
(EQ. 14)
(EQ. 15)
(EQ. 16)
through the error amplifier compensation components from
the FB to the COMP pin. This current then flows through the
feedback resistor, R FB , and can cause the output voltage to
overshoot or undershoot at the end of the VID transition. In
order to ensure the smooth transition of the output voltage
20
Advanced Adaptive Zero Shoot-Through Deadtime
Control (Patent Pending)
The integrated drivers incorporate a unique adaptive deadtime
control technique to minimize deadtime, resulting in high
FN6880.2
May 14, 2010
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6324ACRZR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONTROLLER, CORE+NORTHBRIDGE, PROG PSI, 3.4MHZ SVI - Rail/Tube 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324ACRZ-T | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324ACRZ-TR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONT., CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ SVI, 5 - Tape and Reel 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324AIRZ | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324AIRZR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONTROLLER, CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ S - Rail/Tube 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
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