参数资料
| 型号： | ISL6324ACRZ |
| 厂商： | Intersil |
| 文件页数： | 30/40页 |
| 文件大小： | 0K |
| 描述： | IC HYBRID CTRLR PWM DUAL 48QFN |
| 标准包装： | 43 |
| 应用： | 控制器，AMD SVI |
| 输入电压： | 5 V ~ 12 V |
| 输出数： | 2 |
| 输出电压： | 最高 2V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 供应商设备封装： | 48-QFN（7x7） |
| 包装： | 管件 |
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ISL6324A
C BOOT_CAP ≥ --------------------------------------
Q G1 ? PVCC
Q GATE = ------------------------------------ ? N Q1
Upper MOSFET losses can be divided into separate
components involving the upper-MOSFET switching times,
the lower-MOSFET body-diode reverse recovery charge, Q rr ,
and the upper MOSFET r DS(ON) conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
Q GATE
Δ V BOOT_CAP
V GS1
(EQ. 25)
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 21,
the required time for this commutation is t 1 and the
approximated associated power loss is P UP(1) .
where Q G1 is the amount of gate charge per upper MOSFET
at V GS1 gate-source voltage and N Q1 is the number of
control MOSFETs. The Δ V BOOT_CAP term is defined as the
allowable droop in the rail of the upper gate drive.
1.6
1.4
I M
I P –
P UP ( 1 ) ≈ V IN ? ? ------ + ------------- P - ? ? ? ---- 1 ? ? f S
? N 2 ? ? 2 ?
? t ?
(EQ. 21)
1.2
1.0
At turn-on, the upper MOSFET begins to conduct and this
transition occurs over a time t 2 . In Equation 22, the
0.8
P UP ( 2 ) ≈ V IN ? ? ------ – ------------- P - ? ? ? ---- 2 ? ? f S
approximate power loss is P UP(2) .
? I M I P – ? ? t ?
? N 2 ? ? 2 ?
A third component involves the lower MOSFET
(EQ. 22)
0.6
0.4
0.2
20nC
Q GATE = 100nC
50nC
reverse-recovery charge, Q rr . Since the inductor current has
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q rr , it is
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P UP(3) as shown in
Equation 23.
Δ V BOOT_CAP (V)
FIGURE 18. BOOTSTRAP CAPACITANCE vs BOOT RIPPLE
VOLTAGE
Gate Drive Voltage Versatility
P UP ( 3 ) = V IN ? Q rr ? f S
(EQ. 23)
The ISL6324A provides the user flexibility in choosing the
gate drive voltage for efficiency optimization. The controller
Finally, the resistive part of the upper MOSFET is given in
ties the upper and lower drive rails together. Simply applying
I P – 2
? I M ?
P UP ( 4 ) ≈ r DS ( ON ) ? ? ------ ? ? d + ------------- P -
Equation 24 as P UP(4) .
? N ? 12
2
(EQ. 24)
a voltage from 5V up to 12V on PVCC sets both gate drive
rail voltages simultaneously.
Package Power Dissipation
When choosing MOSFETs it is important to consider the
The total power dissipated by the upper MOSFET at full load
can now be approximated as the summation of the results
from Equations 21, 22, 23 and 24. Since the power
equations depend on MOSFET parameters, choosing the
correct MOSFETs can be an iterative process involving
repetitive solutions to the loss equations for different
MOSFETs and different switching frequencies.
Internal Bootstrap Device
All three integrated drivers feature an internal bootstrap
Schottky diode. Simply adding an external capacitor across
the BOOT and PHASE pins completes the bootstrap circuit.
The bootstrap function is also designed to prevent the
bootstrap capacitor from overcharging due to the large
negative swing at the PHASE node. This reduces voltage
stress on the boot to phase pins.
The bootstrap capacitor must have a maximum voltage
rating above PVCC + 4V and its capacitance value can be
chosen from Equation 25:
30
amount of power being dissipated in the integrated drivers
located in the controller. Since there are a total of three
drivers in the controller package, the total power dissipated
by all three drivers must be less than the maximum
allowable power dissipation for the QFN package.
Calculating the power dissipation in the drivers for a desired
application is critical to ensure safe operation. Exceeding the
maximum allowable power dissipation level will push the IC
beyond the maximum recommended operating junction
temperature of +125°C. The maximum allowable IC power
dissipation for the 7x7 QFN package is approximately 3.5W
When designing the ISL6324A into an application, it is
recommended that the following calculations is used to
ensure safe operation at the desired frequency for the
selected MOSFETs. The total gate drive power losses,
P Qg_TOT , due to the gate charge of MOSFETs and the
FN6880.2
May 14, 2010
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相关代理商/技术参数 |
参数描述 |
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| ISL6324ACRZR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONTROLLER, CORE+NORTHBRIDGE, PROG PSI, 3.4MHZ SVI - Rail/Tube 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324ACRZ-T | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324ACRZ-TR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONT., CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ SVI, 5 - Tape and Reel 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
| ISL6324AIRZ | 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:- 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
| ISL6324AIRZR5381 | 制造商:Intersil Corporation 功能描述:4+1 PHASE CONTROLLER, CORE + NORTHBRIDGE, PROG PSI, 3.4MHZ S - Rail/Tube 制造商:Intersil Corporation 功能描述:IC HYBRID CTRLR PWM DUAL 48QFN |
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