参数资料
型号: ISL6324ACRZ
厂商: Intersil
文件页数: 31/40页
文件大小: 0K
描述: IC HYBRID CTRLR PWM DUAL 48QFN
标准包装: 43
应用: 控制器,AMD SVI
输入电压: 5 V ~ 12 V
输出数: 2
输出电压: 最高 2V
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘
供应商设备封装: 48-QFN(7x7)
包装: 管件
ISL6324A
integrated driver ’s internal circuitry and their corresponding
average driver current can be estimated with Equations 26
and 27, respectively.
The total gate drive power losses are dissipated among the
resistive components along the transition path and in the
bootstrap diode. The portion of the total power dissipated in
P Qg_Q1 = --- ? Q G1 ? PVCC ? f SW ? N Q1 ? N PHASE
P Qg_TOT = P Qg_Q1 + P Qg_Q2 + I Q ? VCC
3
2
P Qg_Q2 = Q G2 ? PVCC ? f SW ? N Q2 ? N PHASE
(EQ. 26)
the controller itself is the power dissipated in the upper drive
path resistance (P DR_UP ) the lower drive path resistance
(P DR_UP ) and in the boot strap diode (P BOOT ). The rest of
the power will be dissipated by the external gate resistors
(R G1 and R G2 ) and the internal gate resistors (R GI1 and
R GI2 ) of the MOSFETs. Figures 19 and 20 show the typical
I DR = ? --- ? Q G1 ? N
3
? 2
Q1
?
+ Q G2 ? N Q2 ? ? N PHASE ? f SW + I Q (EQ. 27)
upper and lower gate drives turn-on transition path. The total
power dissipation in the controller itself, P DR , can be roughly
In Equations 26 and 27, P Qg_Q1 is the total upper gate drive
power loss and P Qg_Q2 is the total lower gate drive power
estimated as Equation 28:
P DR = P DR_UP + P DR_LOW + P BOOT + ( I Q ? VCC )
P BOOT = ---------------------
loss; the gate charge (Q G1 and Q G2 ) is defined at the
particular gate to source drive voltage PVCC in the
corresponding MOSFET data sheet; I Q is the driver total
P Qg_Q1
3
(EQ. 28)
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI1 + R EXT1 R LO1 + R EXT1 ?
P DR_LOW = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI2 + R EXT2 R LO2 + R EXT2 ?
quiescent current with no load at both drive outputs; N Q1 and
N Q2 are the number of upper and lower MOSFETs per phase,
respectively; N PHASE is the number of active phases. The
I Q *VCC product is the quiescent power of the controller
without capacitive load and is typically 75mW at 300kHz.
? R HI1 R LO1 ? P Qg_Q1
? R HI2 R LO2 ? P Qg_Q2
3
2
R EXT1 = R G1 + -------------
N
R EXT2 = R G2 + -------------
N
PVCC
BOOT
D
R GI1
Q1
R GI2
Q2
R HI1
R LO1
UGATE
G
R G1
C GD
R GI1
C GS
S
C DS
Q1
Inductor DCR Current Sensing Component
Selection and R SET Value Calculation
With the single R SET resistor setting the value of the
effective internal sense resistors for both the North Bridge
and Core regulators, it is important to set the R SET value
and the inductor RC filter gain, K, properly. See “Continuous
PHASE
FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
C GD
Balance” on page 15 for more details on the application of
the R SET resistor and the RC filter gain.
There are 3 separate cases to consider when calculating
these component values. If the system under design will
never utilize the North Bridge regulator and the ISL6323 will
R HI2
R LO2
LGATE
G
R G2
R GI2
C GS
C DS
Q2
always be in parallel mode, then follow the instructions for
Case 3 and only calculate values for Core regulator
components.
For all three cases, use the expected VID voltage that would
S
be used at TDC for Core and North Bridge for the V CORE
and V NB variables, respectively.
I NB
I Core
? DCR NB < -------------------------- ? DCR Core
FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
CASE 1
MAX
MAX
N
(EQ. 29)
In Case 1, the DC voltage across the North Bridge inductor
at full load is less than the DC voltage across a single phase
of the Core regulator while at full load. Here, the DC voltage
across the Core inductors must be scaled down to match the
DC voltage across the North Bridge inductor, which will be
impressed across the ISEN_NB pins without any gain. Thus,
31
FN6880.2
May 14, 2010
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