参数资料
型号: ISL6327IRZ-T
厂商: Intersil
文件页数: 17/29页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 48-QFN
标准包装: 4,000
PWM 型: 控制器
输出数: 6
频率 - 最大: 1MHz
占空比: 25%
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 48-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL6327
TABLE 3. VR11 VID 8-BIT (Continued)
Figure 5 shows a current proportional to the average current
VID7
VID6
VID5
VID4
VID3
VID2
VID1
VID0 VOLTAGE
of all active channels, I AVG , flows from FB through a load-
1
1
1
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
1
1
0
0
1
0
0.72500
0.71875
0.71250
line regulation resistor R FB . The resulting voltage drop
across R FB is proportional to the output current, effectively
creating an output voltage droop with a steady-state value
defined using Equation 8:
1
0
0
1
0
0
0
1
0.70625
V DROOP = I AVG R FB
(EQ. 8)
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
0.70000
0.69375
0.68750
0.68125
0.67500
The regulated output voltage is reduced by the droop voltage
V DROOP . The output voltage as a function of load current is
derived by combining Equation 8 with the appropriate
sample current expression defined by the current sense
method employed in Equation 9.
V OUT = V REF – V OFS – ? ------------- ------------------ R FB ?
1
1
0
0
0
0
1
1
0
1
1
0
1
0
1
0
0.66875
0.66250
? I OUT R X ?
? N R ISEN ?
(EQ. 9)
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0.65625
0.65000
0.64375
0.63750
0.63125
0.62500
0.61875
Where V REF is the reference voltage, V OFS is the
programmed offset voltage, I OUT is the total output current
of the converter, R ISEN is the sense resistor connected to
the ISEN+ pin, and R FB is the feedback resistor, N is the
active channel number, and R X is the DCR, or R SENSE
depending on the sensing method.
Therefore the equivalent loadline impedance (i.e. Droop
impedance) is equal to:
R LL = ------------ ------------------
R ISEN
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0.61250
0.60625
0.60000
R FB R X
N
(EQ. 10)
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
0
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0.59375
0.58750
0.58125
0.57500
0.56875
0.56250
0.55625
0.55000
0.54375
0.53750
0.53125
Output-Voltage Offset Programming
The ISL6327 allows the designer to accurately adjust the
offset voltage. When a resistor, R OFS , is connected between
OFS to VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I OFS ) to flow into OFS. If
R OFS is connected to ground, the voltage across it is
regulated to 0.4V, and I OFS flows out of OFS. A resistor
between DAC and REF, R REF , is selected so that the
product (I OFS x R OFS ) is equal to the desired offset voltage.
These functions are shown in Figure 6.
Once the desired output offset voltage has been determined,
use Equation 11 to set R OFS :
For Positive Offset (connect R OFS to VCC):
R OFS = ------------------------------
R OFS = ------------------------------
1
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
1
1
1
0
1
0
1
0
0
1
0.52500
0.51875
0.51250
0.50625
0.50000
OFF
OFF
1.6 × R REF
V OFFSET
For Negative Offset (connect R OFS to GND):
0.4 × R REF
V OFFSET
(EQ. 11)
(EQ. 12)
17
FN9276.4
May 5, 2008
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