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参数资料
| 型号： | ISL6327IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 27/29页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 48-QFN |
| 标准包装： | 4,000 |
| PWM 型： | 控制器 |
| 输出数： | 6 |
| 频率 - 最大： | 1MHz |
| 占空比： | 25% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ISL6327
– N V OUT ? V OUT
? V
L ≥ ( ESR ) ------------------------------------------------------------
? IN ?
f S V IN V P – P ( MAX )
(EQ. 38)
0.3
transient, the capacitor voltage becomes slightly depleted.
The output inductors must be capable of assuming the entire
load current before the output voltage decreases more than
Δ V MAX . This places an upper limit on inductance.
Equation 39 gives the upper limit on L for the cases when
the trailing edge of the current transient causes a greater
output-voltage deviation than the leading edge. Equation 40
addresses the leading edge. Normally, the trailing edge
dictates the selection of L because duty cycles are usually
less than 50%. Nevertheless, both inequalities should be
evaluated, and L should be selected based on the lower of
the two results. In each equation, L is the per-channel
inductance, C is the total output capacitance, and N is the
number of active channels.
0.2
0.1
I L(P-P) = 0
I L(P-P) = 0.5 I O
I L(P-P) = 0.75 I O
0
0 0.2 0.4 0.6 0.8 1.0
DUTY CYCLE (V O /V IN )
FIGURE 19. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 2-PHASE CONVERTER
L ≤ --------------------- Δ V MAX – Δ I ( ESR )
2NCV O
( Δ I ) 2
(EQ. 39)
0.3
I L(P-P) = 0
I L(P-P) = 0.5 I O
I L(P-P) = 0.25 I O
I L(P-P) = 0.75 I O
L ≤ -------------------------- Δ V MAX – Δ I ( ESR ) ? V IN – V O ?
( Δ I ) 2
( 1.25 ) NC
? ?
(EQ. 40)
0.2
Switching Frequency
There are a number of variables to consider when choosing
the switching frequency, as there are considerable effects on
the upper-MOSFET loss calculation. These effects are
outlined in “MOSFETs” on page 23, and they establish the
upper limit for the switching frequency. The lower limit is
established by the requirement for fast transient response and
0.1
small output-voltage ripple as outlined in “Output Filter
0
0
0.2
0.4
0.6
0.8
1.0
Design” on page 26. Choose the lowest switching frequency
that allows the regulator to meet the transient-response
requirements.
Switching frequency is determined by the selection of the
frequency-setting resistor, R T (see the figures labelled
“Typical Application” on page 4 and page 5). Equation 3 is
provided to assist in selecting the correct value for R T .
Input Capacitor Selection
The input capacitors are responsible for sourcing the AC
component of the input current flowing into the upper
MOSFETs. Their RMS current capacity must be sufficient to
handle the AC component of the current drawn by the upper
MOSFETs that is related to duty cycle and the number of
active phases.
For a two phase design, use Figure 19 to determine the
input-capacitor RMS current requirement given the duty
cycle, maximum sustained output current (I O ), and the ratio
of the per-phase peak-to-peak inductor current (I L,PP ) to I O .
Select a bulk capacitor with a ripple current rating which will
minimize the total number of input capacitors required to
support the RMS current calculated. The voltage rating of
the capacitors should also be at least 1.25 times greater
than the maximum input voltage.
27
DUTY CYCLE (V O/ V IN )
FIGURE 20. NORMALIZED INPUT-CAPACITOR RMS CURRENT
vs DUTY CYCLE FOR 3-PHASE CONVERTER
Figures 20 and 21 provide the same input RMS current
information for three and four phase designs respectively.
Use the same approach to selecting the bulk capacitor type
and number as described previously.
Low capacitance, high-frequency ceramic capacitors are
needed in addition to the bulk capacitors to suppress leading
and falling edge voltage spikes. They result from the high
current slew rates produced by the upper MOSFETs turning on
and off. Select low ESL ceramic capacitors and place one as
close as possible to each upper MOSFET drain to minimize
board parasitic impedances and maximize suppression.
MULTIPHASE RMS IMPROVEMENT
Figure 22 is provided as a reference to demonstrate the
dramatic reductions in input-capacitor RMS current upon the
implementation of the multiphase topology. For example,
compare the input RMS current requirements of a two-phase
converter versus that of a single phase. Assume both
converters have a duty cycle of 0.25, maximum sustained
output current of 40A, and a ratio of I L(P-P) to I O of 0.5. The
single phase converter would require 17.3A RMS current
FN9276.4
May 5, 2008
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| ISL6328ACRZ-T | 功能描述:IC VOLTAGE REGULATOR RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - 专用型 系列:* 标准包装:43 系列:- 应用:控制器，Intel VR11 输入电压:5 V ~ 12 V 输出数:1 输出电压:0.5 V ~ 1.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-VFQFN 裸露焊盘 供应商设备封装:48-QFN（7x7） 包装:管件 |
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