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参数资料
| 型号： | ISL6327IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 19/29页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 48-QFN |
| 标准包装： | 4,000 |
| PWM 型： | 控制器 |
| 输出数： | 6 |
| 频率 - 最大： | 1MHz |
| 占空比： | 25% |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 48-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ISL6327
Soft-Start
ISL6327 based VR has 4 periods during soft-start as shown
in Figure 8. After VCC, EN_VTT and EN_PWR reach their
POR/enable thresholds, The controller will have fixed delay
period t D1 . After this delay period, the VR will begin first soft-
start ramp until the output voltage reaches 1.1V VBOOT
voltage. Then, the controller will regulate the VR voltage at
1.1V for another fixed period t D3 . At the end of t D3 period,
ISL6327 reads the VID signals. If the VID code is valid,
ISL6327 will initiate the second soft-start ramp until the
voltage reaches the VID voltage minus offset voltage.
VOUT, 500mV/DIV
After the DAC voltage reaches the final VID setting,
VR_RDY will be set to high with the fixed delay t D5 . The
typical value for t D5 is 85μs.
Fault Monitoring and Protection
The ISL6327 actively monitors output voltage and current to
detect fault conditions. Fault monitors trigger protective
measures to prevent damage to a microprocessor load. One
common power good indicator is provided for linking to external
system monitors. The schematic in Figure 9 outlines the
interaction between the fault monitors and the VR_RDY signal.
VR_RDY Signal
The VR_RDY pin is an open-drain logic output to indicate
that the soft-start period is completed and the output voltage
is within the regulated range. VR_RDY is pulled low during
shutdown and releases high after a successful soft-start and
a fix delay time, t D5 . VR_RDY will be pulled low when an
tD1
t D2
t D3
t D4
t D5
undervoltage, overvoltage, or overcurrent condition is
detected, or the controller is disabled by a reset from
EN_PWR, EN_VTT, POR, or VID OFF-code.
EN_VTT
VR_RDY
VR_RDY
500μs/DIV
UV
FIGURE 8. SOFT-START WAVEFORMS
50%
t SS = t D1 + t D2 + t D3 + t D4
The soft-start time is the sum of the 4 periods as shown in
Equation 14:
(EQ. 14)
t D1 is a fixed delay with the typical value as 1.36ms. t D3 is
determined by the fixed 85μs plus the time to obtain valid
VID voltage. If the VID is valid before the output reaches the
VDIFF
DAC
SOFT-START, FAULT
AND CONTROL LOGIC
+
OV
-
-
OC
+
85μA
I AVG
1.1V, the minimum time to validate the VID input is 500ns.
Therefore the minimum t D3 is about 86μs.
During t D2 and t D4 , ISL6327 digitally controls the DAC
voltage change at 6.25mV per step. The time for each step is
determined by the frequency of the soft-start oscillator which
is defined by the resistor R SS from SS pin to GND. The two
soft-start ramp times t D2 and t D4 can be calculated based on
Equations 15 and 16:
VID + 0.175V
FIGURE 9. VR_RDY AND PROTECTION CIRCUITRY
Undervoltage Detection
The undervoltage threshold is set at 50% of the VID voltage.
When the output voltage at VSEN is below the undervoltage
threshold, VR_RDY gets pulled low. When the output
t D2 = ------------------------ ( μ s )
t D4 = ------------------------------------------------ ( μ s )
1.1xR SS
6.25x25
( V VID – 1.1 ) xR SS
6.25x25
(EQ. 15)
(EQ. 16)
voltage comes back to 60% of the VID voltage, VR_RDY will
return back to high.
Overvoltage Protection
Regardless of the VR being enabled or not, the ISL6327
overvoltage protection (OVP) circuit will be active after its
For example, when VID is set to 1.5V and the R SS is set at
100k Ω , the first soft-start ramp time t D2 will be 704μs and the
second soft-start ramp time t D4 will be 256μs.
19
POR. The OVP thresholds are different under different
operation conditions. When VR is not enabled and before
the 2nd soft-start, the OVP threshold is 1.275V. Once the
controller detects a valid VID input, the OVP trip point will be
changed to the VID voltage plus 175mV.
FN9276.4
May 5, 2008
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