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参数资料
| 型号： | ISL6341IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 12/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 10-TDFN |
| 标准包装： | 6,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 330kHz |
| 占空比： | 85% |
| 电源电压： | 4.5 V ~ 14.4 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6341, ISL6341A, ISL6341B, ISL6341C
repeated. If V OUT = 0.8V, then R OFFSET can be left open.
Output voltages less than 0.8V are not available.
If V IN powers up first, Q 1 will be on, turning Q 2 off; so the
ISL6341x will start-up as soon as V CC comes up. The
( R S + R O )
V OUT = 0.8V ? ---------------------------
R O = ----------------------------------
R O
R S ? 0.8V
V OUT – 0.8V
(EQ. 2)
V ENABLE trip point is 0.7V nominal, so a wide variety of
NFET’s or NPN’s or even some logic IC’s can be used as Q 1
or Q 2 . But Q 2 should pull down hard when on, and must be
low leakage when off (open-drain or open-collector) so as
not to interfere with the COMP output. The V th (or V be ) of Q 2
The VOS pin is expected to see the same ratio for its resistor
divider; R VOS1 should also be chosen in the 1k Ω to 5k Ω
(±1% for accuracy) range. To simplify the BOM, R VOS1
should match R S , and R VOS2 should match R OFFSET .
If margining (or similar programmability) is added externally
(using a switch to change the effective lower resistor value),
the same method may be needed on the VOS pin resistor
divider. If the new VOUT (FB) is shifted too much compared
to the VOS trip, then PGOOD or UV/OV will be more likely to
trip in one direction (and less likely in the other).
Input Voltage Considerations
The “Typical Application” diagram on page 3 shows a
standard configuration where V CC is 5V to 12V, which
includes the standard 5V (±10%) or 12V (±20%) power
supply ranges. The gate drivers use the V CC voltage for
LGATE, and V GD (also 5V to 12V) for BOOT/UGATE. There
is an internal 5V regulator for bias.
The V IN to the upper MOSFET can share the same supply
as V CC , but can also run off a separate supply or other
sources, such as outputs of other regulators. If V CC powers
up first, and the V IN or V GD are not present by the time the
initialization is done, then undervoltage will trip at the end of
soft-start (and will not recover without toggling V CC ; toggling
COMP/EN will not restart it). Therefore, either the supplies
must be turned on in the proper order (together, or V CC last),
or the COMP/EN pin should be used to disable V OUT until all
supplies are ready.
Figure 10 shows a simple sequencer for this situation. If V CC
powers up first, Q 1 will be off and R 3 pulling to V CC will turn
Q 2 on, keeping the ISL6341x in shut-down. When V IN turns
on, the resistor divider R 1 and R 2 determines when Q 1 turns
on, which will turn off Q 2 , and release the shut-down.
should be reviewed over process and temperature variations
to insure that it will work properly under all conditions. Q 2
should be placed near the COMP/EN pin.
The V IN range can be as low as ~1.5V (for V OUT as low as
the 0.8V reference). It can be as high as 20V (for V OUT just
below V IN , limited by the maximum duty cycle). There are
some restrictions for running high V IN voltage.
The first consideration for high V IN is the maximum BOOT
voltage of 36V. The V IN (as seen on PHASE) plus V GD (boot
voltage - minus the diode drop), plus any ringing (or other
transients) on the BOOT pin must be less than 36V. If V IN is
20V, that limits V GD plus ringing to 16V.
The second consideration is the maximum voltage ratings
for V CC and BOOT-PHASE (for V GD ); both are set at 15V. If
V IN is above the maximum operating range for V CC of
14.4V, then both V CC and V GD need to be supplied
separately. They can be derived from V IN (using a linear
regulator or equivalent), or they can be independent. In
either case, they must satisfy the power supply sequencing
requirements noted earlier (either power-up in the proper
order, or use a sequencer to disable the output until they are
all ready).
The third consideration for high V IN is duty cycle. Very low
duty cycles (such as 20V in to 1.0V out, for 5% duty cycle)
require component selection compatible with that choice
(such as low r DS(ON) lower MOSFET, a good LC output
filter, and compensation values to match). At the other
extreme (for example, 20V in to 12V out), the upper
MOSFET needs to be lower r DS(ON) . There is also the
maximum duty cycle restriction. In all cases, the input and
output capacitors and both MOSFETs must be rated for the
voltages present.
V IN
V CC
Application Guidelines
Layout Considerations
R 1
R 2
R 3
Q 1
TO COMP/EN
Q 2
As in any high frequency switching converter, layout is very
important. Switching current from one power device to another
can generate voltage transients across the impedances of the
interconnecting bond wires and circuit traces. These
interconnecting impedances should be minimized by using
FIGURE 10. SEQUENCER CIRCUIT
12
wide, short printed circuit traces. The critical components
should be located as close together as possible, using ground
plane construction or single point grounding.
FN6538.2
December 2, 2008
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6353CRTZ | 功能描述:电流型 PWM 控制器 VR12 MEMORY CNTRLR 3 PHS 2 INT 5V DRVRS RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6353CRTZ-T | 功能描述:电流型 PWM 控制器 VR12 MEMORY CNTRLR 3 PHS 2 INT 5V DRVRS RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6353CRTZ-TS2568 | 制造商:Intersil Corporation 功能描述:INTEL, ISL6353CRTZ-T W/BARCODE LABELS, 12 MONTH D/C RESTRICT - Tape and Reel |
| ISL6353CRZ | 制造商:Intersil 功能描述:Multiphase PWM Regulator for VR12 DDR Memory Systems |
| ISL6353IRTZ | 功能描述:电流型 PWM 控制器 VR12 MEMORY CNTRLR 3 PHS 2 INT 5V DRVRS RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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