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参数资料
| 型号： | ISL6341IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 7/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 10-TDFN |
| 标准包装： | 6,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 330kHz |
| 占空比： | 85% |
| 电源电压： | 4.5 V ~ 14.4 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6341, ISL6341A, ISL6341B, ISL6341C
.
LGATE
STARTS
SWITCHING
V OUT OVERCHARGED
0.7V
COMP/EN (0.25V/DIV)
V OUT
(0.25V/DIV)
LGATE/OCSET
0.25V/DIV
PGOOD (2V/DIV)
V OUT PRE-BIASED
GND>
GND>
V OUT NORMAL
t0
t1
t2
t3
t4
t0
t1
t2
4.0ms
0.8ms
4.0ms
FIGURE 3. SOFT-START WITH PRE-BIAS
FIGURE 2. LGATE/OCSET AND SOFT-START OPERATION
From t1, there is a nominal 4ms delay, which allows the VCC
pin to rise. At the same time, the LGATE/OCSET pin is
initialized by disabling the LGATE driver and drawing I OCSET
(nominal 10μA) through R OCSET . This sets up a voltage that
will represent the OCSET trip point for the OCP sample and
hold operation. The sample and hold uses a digital counter and
DAC (to save the voltage so the stored value does not degrade)
for as long as the V CC is above V POR . See “Overcurrent
and variables. Upon the completion of sample and hold at t2,
the soft-start operation is initiated (around 0.8ms delay to t3),
and then around 4ms for the output voltage to ramp up (0% to
100%) between t3 and t4. The PGOOD output is allowed to go
high at t4 if VOS (and thus V OUT ) is within the PGOOD
window.
Soft-Start and Pre-Biased Outputs
Functionally, the soft-start internally ramps the reference on the
non-inverting terminal of the error amp from zero to 0.8V in a
nominal 4ms. The output voltage will thus follow the ramp, from
zero to final value, in the same 4ms. The ramp is created
digitally, so there will be small discrete steps. There is no simple
way to change this ramp rate externally, as it is fixed by the
300kHz (or 600kHz) switching frequency (and the ramp and
delay time is the same for both frequencies).
After an initialization period (t2 to t3), the error amplifier
(COMP/EN pin) is enabled, and begins to regulate the
converter’s output voltage during soft-start. The oscillator’s
triangular waveform is compared to the ramping error amplifier
voltage. This generates PHASE pulses of increasing width that
charge the output capacitors. When the internally generated
soft-start voltage exceeds the reference voltage (0.8V), the
soft-start is complete, and the output should be in regulation at
the expected voltage. This method provides a rapid and
controlled output voltage rise; there is no large in-rush current
charging the output capacitors. The entire start-up sequence
from POR typically takes 9ms; 5ms for the delay and OCP
sample, and 4ms for the soft-start ramp.
7
Figure 3 shows the normal V OUT curve in blue; initialization
begins at t0, and the output ramps between t1 and t2. If the
output is pre-biased to a voltage less than the expected
value (as shown by the magenta curve), the ISL6341x will
detect that condition. Neither MOSFET will turn-on until the
soft-start ramp voltage exceeds the output; V OUT starts
seamlessly ramping from there.
There is a restriction for the pre-bias case; if the pre-biased
V OUT is greater than V GD , then the boot cap may get
discharged, and will not be able to restart. For example, if
V IN = 12V, V OUT = 8V and prebiased to 6V, and V GD is only
5V, then the voltage left on the boot cap (to UGATE) will not
be able to turn on the upper FET. The simple solution here is
to use the 12V for V GD . The guideline is to make V GD -
diode - Vth upper FET > V OUT to prevent this condition.
If the output is pre-biased to a voltage above the expected
value (as in the red curve), neither MOSFET will turn-on until
the end of the soft-start, at which time it will pull the output
voltage quickly down to the final value. Any resistive load
connected to the output will help pull-down the voltage (at
the RC rate of the R of the load and the C of the output
capacitance).
One exception to the overcharged case is if the pre-bias is
high enough to trip OV protection (>1V on VOS); then
LGATE will pulse to try to pull V OUT lower. The IC will remain
latched in this mode until V CC power is toggled.
If the V IN to the upper MOSFET drain (or the V GD voltage to
the boot diode) is from a different supply that comes up after
V CC , the soft-start would start its cycle, but with no output
voltage ramp. Once the undervoltage protection is enabled
(at the end of the soft-start ramp), the output will latch off.
Therefore, for normal operation, V IN (and V GD ) must be high
enough before or with V CC . If this is not possible, then the
alternative is add sequencing logic to the COMP/EN pin to
delay the soft-start until the V IN (and V GD ) supply is ready
(see “Input Voltage Considerations” on page 12).
FN6538.2
December 2, 2008
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