参数资料
型号: ISL6341IRZ-T
厂商: Intersil
文件页数: 13/17页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM VM 10-TDFN
标准包装: 6,000
PWM 型: 电压模式
输出数: 1
频率 - 最大: 330kHz
占空比: 85%
电源电压: 4.5 V ~ 14.4 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 85°C
封装/外壳: 10-WFDFN 裸露焊盘
包装: 带卷 (TR)
ISL6341, ISL6341A, ISL6341B, ISL6341C
.
Feedback Compensation
ISL6341x
V IN
This section highlights the design consideration for a
voltage-mode controller requiring external compensation. To
address a broad range of applications, a type-3 feedback
UGATE
PHASE
LGATE/OCSET
Q 1
Q 2
L O
C IN
C O
V OUT
network is recommended, as shown in the top part of
Figure 13.
Figure 13 also highlights the voltage-mode control loop for a
synchronous-rectified buck converter, applicable to the
ISL6341x circuit. The output voltage (V OUT ) is regulated to
RETURN
FIGURE 11. PRINTED CIRCUIT BOARD POWER AND
GROUND PLANES OR ISLANDS
Figure 11 shows the critical power components of the
converter. To minimize the voltage overshoot, the
interconnecting wires indicated by heavy lines should be part of
a ground or power plane in a printed circuit board. The
components shown should be located as close together as
possible. Please note that the capacitors C IN and C O may each
represent numerous physical capacitors. For best results,
locate the ISL6341x within 1 inch of the MOSFETs, Q 1 and Q 2 .
The circuit traces for the MOSFET gate and source
connections from the ISL6341x must be sized to handle up to
2A peak current.
the reference voltage, V REF . The error amplifier output
(COMP pin voltage) is compared with the oscillator (OSC)
modified sawtooth wave to provide a pulse-width modulated
wave with an amplitude of V IN at the PHASE node. The
PWM wave is smoothed by the output filter (L and C). The
output filter capacitor bank’s equivalent series resistance is
represented by the series resistor E.
The modulator transfer function is the small-signal transfer
function of V OUT /V COMP . This function is dominated by a DC
gain, given by d MAX V IN /V OSC , and shaped by the output
filter, with a double pole break frequency at F LC and a zero at
F CE . For the purpose of this analysis, L and D represent the
channel inductance and its DCR, while C and E represent the
total output capacitance and its equivalent series resistance.
F LC = ---------------------------
F CE = ------------------------
+V GD
1
2 π ? L ? C
1
2 π ? C ? E
(EQ. 3)
Q 2
V OUT
VOS
COMP/EN
FB
+V CC
VCC
ISL6341x
BOOT
C BOOT
PHASE
LGATE/OCSET
+V IN
Q 1 L O
C O
V OUT
COMP
R2
C2
C1
R3
C3
C VCC
GND
R OCSET
E/A
-
+
FB
Ro
R1
VREF
FIGURE 12. PRINTED CIRCUIT BOARD SMALL SIGNAL
LAYOUT GUIDELINES
Figure 12 shows the circuit traces that require additional
layout consideration. Use single point and ground plane
construction for the circuits shown. Provide local V CC
decoupling between VCC and GND pins. Locate the
capacitor, C BOOT as close as practical to the BOOT and
PHASE pins. Locate the resistor, R OSCET close to the
PWM
CIRCUIT
OSCILLATOR
V OSC
UGATE
V IN
L
V OUT
D
LGATE/OCSET pin because the internal current source is
HALF-BRIDGE
only 10μA. Minimize any leakage current paths on the
DRIVE
PHASE
C
COMP/EN pin. All components used for feedback
compensation and VOS resistor divider (inside the dotted
box) should be located as close to the IC as practical. Near
the load, pick a point V OUT that will be the regulation center;
LGATE
E
run a single unloaded narrow trace from there to the
ISL6341x
EXTERNAL CIRCUIT
compensation components. The same trace can also be
used for VOS divider.
13
FIGURE 13. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
FN6538.2
December 2, 2008
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