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参数资料
| 型号： | ISL6341IRZ-T |
| 厂商： | Intersil |
| 文件页数： | 8/17页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM VM 10-TDFN |
| 标准包装： | 6,000 |
| PWM 型： | 电压模式 |
| 输出数： | 1 |
| 频率 - 最大： | 330kHz |
| 占空比： | 85% |
| 电源电压： | 4.5 V ~ 14.4 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 10-WFDFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
ISL6341, ISL6341A, ISL6341B, ISL6341C
If the IC is disabled after soft-start (by pulling COMP/EN pin
low), and then enabled (by releasing the COMP/EN pin),
then the full initialization (including a new OCP sample) will
take place.
If the output is shorted to GND during soft-start, the OCP will
handle it, as described in the next section.
Overcurrent Protection (OCP)
The overcurrent function protects the converter from a shorted
output by using the lower MOSFET’s ON-resistance, r DS(ON) ,
to monitor the current. A resistor (R OCSET ) programs the
overcurrent trip level (see “Typical Application” on page 3).
This method enhances the converter’s efficiency and reduces
cost by eliminating a current sensing resistor.
Following POR and release of COMP/EN, the ISL6341x
initiates the Overcurrent Protection sample and hold
operation. The LGATE driver is disabled to allow an internal
10μA current source to develop a voltage across R OCSET .
The ISL6341x samples this voltage (which is referenced to
the GND pin) at the LGATE/OCSET pin, and holds it in a
counter and DAC combination. This sampled voltage is held
internally as the Overcurrent Set Point, for as long as power
is applied, or until a new sample is taken after coming out of
a COMP/EN shut-down.
The actual monitoring of the lower MOSFET’s ON-resistance
starts 200ns (nominal) after the edge of the internal PWM logic
signal (that creates the rising external LGATE signal). This is
done to allow the gate transition noise and ringing on the
PHASE pin to settle out before monitoring. The monitoring
ends when the internal PWM edge (and thus LGATE) goes low.
The OCP can be detected anywhere within the above window.
To allow sufficient time to detect OCP, the regulator will limit
the maximum UGATE duty cycle to ~85% at 300kHz (~75%
at 600kHz); there will always be an LGATE pulse of at least
300ns. This minimum width will also act as a boot-refresh
function. If the boot capacitor loses any charge while UGATE
is high, it will be refreshed each cycle while LGATE is high.
The ISL6341x share most of the detection circuitry; the main
difference among them is what happens after detection.
ISL6341, ISL6341B
When overcurrent is detected (while LGATE is high), the logic
will disable UGATE, and leave LGATE high until the current
drops to 1/2 of its programmed OCP value. This may take
several clock cycles, and it keeps the current from building up
too high. Once the current is low enough, UGATE will go high
on the next PWM cycle, and OCP will be monitored when
LGATE goes high. If OCP trips a 2nd time, it will again wait
until the current drops. If it trips for the 3rd time, it will latch off
the output (LGATE and UGATE low). If there is no OCP trip on
one of the retries, then the trip-counter resets to zero, and
three new consecutive cycles are required to latch off.
8
I INDUCTOR (10A/DIV)
OC
1/2 OC
0A>
LGATE (12V/DIV)
GND>
UGATE (24V/DIV)
GND>
FIGURE 4. OCP TIMING (ISL6341, ISL6341B)
Figure 4 shows a typical waveform for the ISL6341,
ISL6341B, where the normal inductor current is around 10A,
and the OCP trip is 16A. This is just an illustration; the actual
shape of the waveforms depends on the component values,
as well as the characteristics of the load and the short. On the
third trip, the gate drivers stop switching, and the current goes
to zero. To recover from this latched off condition, the user
must toggle V CC (power-down and power-up) for a new POR,
or toggle COMP/EN pin to restart (either includes initialization
and soft-start).
As the output inductor current rises and falls, the output
voltage is also affected. Note that in extreme cases during
the three consecutive trips, the UV may actually trip before
the OCP. The IC provides protection in either case, but
perhaps not quite at the programmed current. An OCP trip
can be reset by toggling either POR or COMP/EN, but a UV
trip is only reset by toggling POR. See Table 2 for the
protection summary.
Starting up into a shorted load will be handled the same way;
but the waveforms may look different, since the output is not
yet at its final value. OCP is always enabled during soft-start
(UV is not); it will need the three consecutive trips to latch off.
ISL6341A, ISL6341C
Figure 5 shows the same conditions for the ISL6341A,
ISL6341C. For this version, when overcurrent is first
detected (while LGATE is high), the logic will shut off the
output (LGATE and UGATE both go low), and the current
goes to zero.
It will then go into a “hiccup” mode of infinite retries. After two
dummy soft-start time-outs, a real soft-start will begin. If the
short is still there, it will trip during the soft-start ramp, and
will start another retry cycle. Once the short is removed, the
next real soft-start will be successful, and normal operation
can continue.
FN6538.2
December 2, 2008
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相关代理商/技术参数 |
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| ISL6353CRTZ | 功能描述:电流型 PWM 控制器 VR12 MEMORY CNTRLR 3 PHS 2 INT 5V DRVRS RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
| ISL6353CRTZ-T | 功能描述:电流型 PWM 控制器 VR12 MEMORY CNTRLR 3 PHS 2 INT 5V DRVRS RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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| ISL6353CRZ | 制造商:Intersil 功能描述:Multiphase PWM Regulator for VR12 DDR Memory Systems |
| ISL6353IRTZ | 功能描述:电流型 PWM 控制器 VR12 MEMORY CNTRLR 3 PHS 2 INT 5V DRVRS RoHS:否 制造商:Texas Instruments 开关频率:27 KHz 上升时间: 下降时间: 工作电源电压:6 V to 15 V 工作电源电流:1.5 mA 输出端数量:1 最大工作温度:+ 105 C 安装风格:SMD/SMT 封装 / 箱体:TSSOP-14 |
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