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参数资料
| 型号： | ISL6551ABZ-T |
| 厂商： | Intersil |
| 文件页数： | 13/26页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR FLYBACK PWM 28-SOIC |
| 标准包装： | 1,000 |
| PWM 型： | 电流模式 |
| 输出数： | 6 |
| 频率 - 最大： | 1MHz |
| 占空比： | 50% |
| 电源电压： | 10.8 V ~ 13.2 V |
| 降压： | 无 |
| 升压： | 无 |
| 回扫： | 是 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -40°C ~ 105°C |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 包装： | 带卷 (TR) |
ISL6551
500
450
400
350
300
250
200
150
+18%
-24%
incorporated. The current ramp is blanked out during the
resonant delay period because no switching occurs in the
lower FETs. The leading edge blanking function will not be
activated until the soft-start (CSS) reaches over 400mV, as
illustrated in Figures 4 and 9. The leading edge blanking
(LEB) function can be disabled by tying the R_LEB pin to
VDD, i.e., LEB=1. Never leave the pin floating.
- The blanking time can be estimated with Equation 9,
whose relationship can be seen in Figure 8. The
percentages in the figure are the tolerances at the two
100
+37%
+4%
endpoints of the curve.
50
0
20
40
60
80
100
120
t LEB = 2 x R_LEB / k ? + 15 (ns)
(EQ. 9)
R_RESDLY (k ? )
FIGURE 7. R_RESDLY vs RESDLY
? Leading Edge Blanking (R_LEB)
- In current mode control, the sensed switch (FET) current is
processed in the Ramp Adjust and LEB circuits and then
compared to a control signal (EAO voltage). Spikes, due to
parasitic elements in the bridge circuit, would falsely trigger
the comparator generating the PWM signal. To prevent
false triggering, the leading edge of the sensed current
300
250
200
150
100
50
+51%
-11%
+20%
-18%
signal is blanked out by a period that can be programmed
with the R_LEB resistor. Internal switches gate the analog
input to the PWM comparator, implementing the blanking
function that eliminates response degrading delays which
0
20
40
60
80
R_LEB (k ? )
100
120
140
would be caused if filtering of the current feedback was
FIGURE 8. R_LEB vs t LEB
399K
0.1 μ
VDD
ADJ_RAMP
200mV
ADJ_RAMP
BGREF
RAMP_OUT
(TO PWM
0
ISENSE
COMPARATOR)
R_RA
RAMP_OUT
200mV
R_RA
ISENSE
ADD RAMP
+
-
BLANK
200mV
RESDLY
0
LEB
X
SSL
X
RAMP_OUT
BLANK
R_LEB
R_LEB
SET
BLANKING
TIME
RESDLY
LEB
SSL
(See Fig. 4)
X
1
1
0
1
X
0
X
1
BLANK
NO BLANK
NO BLANK
FIGURE 9. SIMPLIFIED RAMP ADJUST AND LEADING EDGE BLANKING CIRCUITS
13
FN9066.5
January 3, 2006
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISL6551AR | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| ISL6551AR-T | 制造商:Rochester Electronics LLC 功能描述: 制造商:Intersil Corporation 功能描述: |
| ISL6551ARZ | 功能描述:IC REG CTRLR FLYBACK PWM 28-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6551ARZ-T | 功能描述:IC REG CTRLR FLYBACK PWM 28-QFN RoHS:是 类别:集成电路 (IC) >> PMIC - 稳压器 - DC DC 切换控制器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- PWM 型:电流模式 输出数:1 频率 - 最大:275kHz 占空比:50% 电源电压:18 V ~ 110 V 降压:无 升压:无 回扫:无 反相:无 倍增器:无 除法器:无 Cuk:无 隔离:是 工作温度:-40°C ~ 85°C 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 包装:带卷 (TR) |
| ISL6551EVAL1 | 功能描述:EVALUATION BOARD ISL6551 RoHS:否 类别:编程器，开发系统 >> 评估板 - DC/DC 与 AC/DC（离线）SMPS 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:True Shutdown™ 主要目的:DC/DC，步升 输出及类型:1，非隔离 功率 - 输出:- 输出电压:- 电流 - 输出:1A 输入电压:2.5 V ~ 5.5 V 稳压器拓扑结构:升压 频率 - 开关:3MHz 板类型:完全填充 已供物品:板 已用 IC / 零件:MAX8969 |
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