参数资料
型号: ISL6551ABZ-T
厂商: Intersil
文件页数: 18/26页
文件大小: 0K
描述: IC REG CTRLR FLYBACK PWM 28-SOIC
标准包装: 1,000
PWM 型: 电流模式
输出数: 6
频率 - 最大: 1MHz
占空比: 50%
电源电压: 10.8 V ~ 13.2 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 105°C
封装/外壳: 28-SOIC(0.295",7.50mm 宽)
包装: 带卷 (TR)
ISL6551
Current Sense
Primary FETs
Q3_S
T_CURRENT
ISENSE
V IN F
or CURRENT_SEN_P
Q1_G
P–
Q1
Q2_G
P+
Q2
Q4_S
FIGURE 14A. TWO-LEG SENSE
Q3_G
Q3_S
Q3
Q4_G
Q4_S
Q4
FIGURE 15A. FULL BRIDGE
V IN F
ISENSE
CURRENT_SEN_P
P1–
P2–
FIGURE 14B. TOP SENSE
ISENSE
Q3_S & Q4_S
Q3_G
Q3_S
Q3
Q4_G
Q4_S
Q4
RSENSE
FIGURE 14C. RESISTOR SENSE (PRIMARY CONTROL)
Two-Leg Sense - Senses the current that flows through both
lower primary FETs. Operates at the switching frequency.
Top Sense - Senses the sum of the current that flows through
both upper primary FETs. Operates at the clock frequency.
Resistor Sense - This simple scheme is used in a primary side
control system. The sum of the current that flows through both
lower primary FETs is sensed with a low impedance power
resistor. The sources of Q3 and Q4 and ISENSE should be tied
at the same point as close as possible.
BIASES
Linear Regulator - In a primary side control system, a
linear regulator derived from the input line can be used for
the start-up purpose, and an extra winding coupled with the
main transformer can provide the controller power after the
start up.
DCM Flyback - Use a PWM controller to develop both
primary and secondary biases with discontinuous current
mode flyback topology.
18
FIGURE 15B. PUSH-PULL
Full Bridge - Four MOSFETs are required for full bridge
converters. The drain to source voltage rating of the
MOSFETs is Vin.
Push-Pull - Only the two lower MOSFETs are required for
push-pull converters. The two upper drivers are not used.
The V DS of the MOSFETs is 2xVin.
FN9066.5
January 3, 2006
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