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参数资料
| 型号： | ISL8120EVAL3Z |
| 厂商： | Intersil |
| 文件页数： | 25/35页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR ISL8120 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 1.2V，1.2V |
| 电流 - 输出： | 2 x 25A 或 1 x 50A |
| 输入电压： | 3 ~ 22 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 150kHz ~ 1.5MHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL8120 |
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ISL8120
VMON1
113%
conditions of EN/FF = LOW and the output voltage above
113% (all VMON pins and EN pins are tied together) and
87%
EN/FF1
OR
AND
FORCE
LGATE1
HIGH
turns off after the output drops below 87%. Thus, in a high
phase count application (Multiphase Mode), all cascaded
ICs can latch off simultaneously via the EN pins (EN pins are
VMON1>120%
VMON2
113%
87%
EN/FF2
multiphase
MODE = HIGH
OR
OR
AND
AND
FORCE
LGATE2
HIGH
tied together in multiphase mode), and each IC shares the
same sink current to reduce the stress and eliminate the
bouncing among phases.
The UV functionality is not enabled until the end of soft-start.
In a UV event, if the output drops below -13% of the target
level due to some reason (cases when EN/FF is not pulled
low) other than OV, OC, OT, and PLL faults, the lower
MOSFETs will turn off to avoid any negative voltage ringing.
VMON2 > 120%
FIGURE 11. FORCE LGATE HIGH LOGIC
VOUT
120%
Both channels share the same PGOOD output. Either of the
channels indicating out-of-regulation will pull-down the
3 CYCLES
3 CYCLES
PGOOD pin. The Power-Good comparators monitor the
voltage on the VMON pins. The trip points are shown in
PGOOD
UV
OV LATCH
Figure 10. PGOOD will not be asserted until after the
completion of the soft-start cycle of both channels. If
Channels 1 or 2 are not used, the Power-Good can stay in
operation by connecting 2 channels’ VMON pins together.
The PGOOD pulls low upon both EN/FF’s disabling it if one
of the VMON pins’ voltage is out of the threshold window.
PGOOD will not pull low until the fault presents for three
consecutive clock cycles. In Dual/DDR application, if the
turn-off channel pre-charges its VMON within the PGOOD
threshold window, it could indicate Power-Good, however,
the PGOOD signal can pull low with an external PNP or
PMOS transistor via the EN/FF of the corresponding off
channel.
Overvoltage and Undervoltage Protection
The Overvoltage (OV) and Undervoltage (UV) protection
circuitry monitor the voltage on the VMON pins.
OV protection is active from the beginning of soft-start. An
OV condition (>120%) would latch IC off (the high-side
MOSFET to latch off permanently; the low-side MOSFET
turns on immediately at the time of OV trip and then turns off
permanently after the output voltage drops below 87%). The
EN/FF and PGOOD are also latched low at OV event. The
latch condition can be reset only by recycling VCC. In
Dual/DDR mode, each channel is responsible for its own OV
event with the corresponding VMON as the monitor. In
multiphase mode, both channels respond simultaneously
when either triggers an OV event .
There is another non-latch OV protection (113% of target
level). At the condition of EN/FF low and the output over
113% OV, the lower side MOSFET will turn on until the
output drops below 87%. This is to protect the overall power
trains in case of only one channel of a multiphase system
detecting OV. The low-side MOSFET always turns on at the
25
UGATE AND EN/FF LATCH LOW
FIGURE 12. PGOOD TIMING UNDER UV AND OV
PRE-POR Overvoltage Protection (PRE-POR-OVP)
When both the VCC and PVCC are below PORs (not
including EN POR), the UGATE is low and LGATE is floating
(high impedance). EN/FF has no control on LGATE when
below PORs. When above PORs, the LGATE would not be
floating but toggling with its PWM pulses. An internal 10k Ω
resistor, connected in between PHASE and LGATE nodes,
implements the PRE-POR-OVP circuit. The output of the
converter that is equal to phase node voltage via output
inductors is then effectively clamped to the low-side
MOSFET’s gate threshold voltage, which provides some
protection to the microprocessor if the upper MOSFET(s) is
shorted during start-up, shutdown, or normal operations. For
complete protection, the low-side MOSFET should have a
gate threshold that is much smaller than the maximum
voltage rating of the load.
The PRE-POR-OVP works against pre-biased start-up when
pre-charged output voltage is higher than the threshold of
the low-side MOSFET, however, it can be disabled by
placing a 2k resistor from LGATE to ground.
Over-Temperature Protection (OTP)
When the junction temperature of the IC is greater than
+150°C (typically), both EN/FF pins pull low to inform other
cascaded channels via their EN/FF pins. All connected
EN/FFs stay low and release after the IC’s junction
temperature drops below +125°C (typically), with a +25°C
hysteresis (typical).
March 20, 2009
FN6641.0
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