参数资料
型号: ISL8120EVAL3Z
厂商: Intersil
文件页数: 26/35页
文件大小: 0K
描述: EVALUATION BOARD FOR ISL8120
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 2,非隔离
输出电压: 1.2V,1.2V
电流 - 输出: 2 x 25A 或 1 x 50A
输入电压: 3 ~ 22 V
稳压器拓扑结构: 降压
频率 - 开关: 150kHz ~ 1.5MHz
板类型: 完全填充
已供物品:
已用 IC / 零件: ISL8120
ISL8120
Current Loop
When the ISL8120 operates in 2-phase mode, the current
control loop keeps the channel’s current in balance. After
175ns blanking period with respect to the falling edge of the
where IL is the inductor DC current, DCR is its DC
resistance, and t MIN_OFF is 350ns.
For low-side MOSFET r DS(ON) sensing, the ICS can be
derived from Equation 3 :
? IL + ---------------- ? ? ? ---------------- – t MIN_OFF ? ? ? ? r DS ( ON )
? ?
2F SW
PWM pulse of each channel, the voltage developed across
the DCR of the inductor, r DS(ON) of the low-side MOSFETs,
or a precision resistor, is filtered and sampled for 175ns. The
current (I CS1 /I CS2 ) is scaled by the R ISEN resistor and
? V OUT 1 – D ?
L
ICS = --------------------------------------------------------------------------------------------------------------------------
RISEN
(EQ. 3)
? IL + ---------------- ? ? ? ---------------- – t MIN_OFF ? ? ? ? DCR
? ?
2F SW
(EQ. 2)
(EQ. 4)
IAVG = -----------------------------------
provides feedback proportional to the average output current
of each channel.
For DCR sensing, the sampling current ICS can be derived
from Equation 2:
? V OUT 1 – D ?
L
ICS = -----------------------------------------------------------------------------------------------------------------
RISEN
In multiphase mode (VSEN2- pulled high), the scaled output
currents from both active channels are combined to create
an average current reference (IAVG) which represents
average current of both channel outputs as calculated in
Equation 4.
ICS1 + ICS2
2
VOUT
IOUT1
DCR SENSING
PHASE1
VOUT
IOUT1
r DS(ON) SENSING
PHASE1
PHASE2
IOUT2
VOUT
L1
C
DCR1
R
L1
DCR1
DCR2
R
L2
C
R ISEN1
R ISEN1
ISEN1B
VCC
ISEN1A
DCR1
ISEN1B
ISEN1A
ISEN2A
DCR2
AMP
ISEN2B
R ISEN2
700mV
AMP
I CS1
I CS2
VSEN2-
+
-
+
VSEN2+
ISHARE
CHANNEL 1
PWM CONTROL
BLOCK
E/A
I AVG_CS +15μA
CURRENT
SHARE
CHANNEL 1
CURRENT
CORRECTION
BLOCK
-
I CSH_ERR
I AVG_CS
+
2
I AVG
+
-
-
CHANNEL 2
CURRENT
CORRECTION
BLOCK
CHANNEL 2
PWM CONTROL
BLOCK
BLOCK
ISET
R ISET
I AVG_CS +15μA
1.2V
AVG_OC
COMP
CHANNEL 1
SOFT-START &
FAULT LOGIC
I TRIP =108 μ A
OC2
COMP
7 CYCLES
DELAY
CHANNEL 2
SOFT-START &
FAULT LOGIC
V ISHARE
7 CYCLES
DELAY
OC1
COMP
I TRIP =108μA
I AVG = (I CS1 + I CS2 ) / 2
I AVG_CS = I AVG or I CS1
I CSH_ERR = (V ISARE - V ISET )/G CS
FIGURE 13. SIMPLIFIED CURRENT SAMPLING AND OVERCURRENT PROTECTION
26
March 20, 2009
FN6641.0
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