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参数资料
| 型号： | ISL8120EVAL3Z |
| 厂商： | Intersil |
| 文件页数： | 31/35页 |
| 文件大小： | 0K |
| 描述： | EVALUATION BOARD FOR ISL8120 |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 2，非隔离 |
| 输出电压： | 1.2V，1.2V |
| 电流 - 输出： | 2 x 25A 或 1 x 50A |
| 输入电压： | 3 ~ 22 V |
| 稳压器拓扑结构： | 降压 |
| 频率 - 开关： | 150kHz ~ 1.5MHz |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | ISL8120 |
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ISL8120
P DR_UP = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI1 + R EXT1 R LO1 + R EXT1 ?
P DR_LOW = ? -------------------------------------- + ---------------------------------------- ? ? ---------------------
? R HI2 + R EXT2 R LO2 + R EXT2 ?
P Qg_Q1 = --------------------------------------- ? F SW ? N Q1
Q G2
P Qg_Q2 = --------------------------------------- ? F SW ? N Q2
P DR = P DR_UP + P DR_LOW
? R HI1 R LO1 ? P Qg_Q1
? R HI2 R LO2 ? P Qg_Q2
Q G1 ? PVCC 2
V GS1
? PVCC 2
V GS2
2
2
(EQ. 8)
Oscillator
The Oscillator is a sawtooth waveform, providing for leading
edge modulation with 350ns minimum dead time. The
oscillator (Sawtooth) waveform has a DC offset of 1.0V.
Each channel’s peak-to-peak of the ramp amplitude is set
proportional the voltage applied to its corresponding EN/FF
1,600
1,400
1,200
1,000
R EXT2 = R G1 + -------------
R EXT2 = R G2 + -------------
R GI1
N Q1
R GI2
N Q2
800
600
where the gate charge (Q G1 and Q G2 ) is defined at a
400
particular gate to source voltage (V GS1 and V GS2 ) in the
corresponding MOSFET datasheet; I Q_VIN is the driver ’s
total quiescent current with no load at drive outputs; N Q1 and
N Q2 are number of upper and lower MOSFETs, respectively.
200
0
20 40
60 80 100 120 140 160 180 200 220 240 260
R_FS (k Ω )
To keep the IC within its operating temperature range, an
external power resistor could be used in series with VIN pin
to bring the heat out of the IC, or and external LDO could be
used when necessary.
FIGURE 21. R FS vs SWITCHING FREQUENCY
Frequency Synchronization and Phase Lock Loop
The FSYNC pin has two primary capabilities: fixed frequency
operation and synchronized frequency operation. By tying a
PVCC
BOOT
D
resistor (R FSYNC ) to GND from the FSYNC pin, the switching
frequency can be set at any frequency between 150kHz and
R HI1
G
C GD
C DS
1.5MHz. The frequency setting curve shown in Figure 21 is
provided to assist in selecting the correct value for R FSYNC .
By connecting the FSYNC pin to an external square pulse
R LO1
UGATE
R G1
R GI1
C GS
Q1
waveform (such as the CLOCK signal, typically 50% duty
cycle from another ISL8120), the ISL8120 will synchronize
S
PHASE
FIGURE 19. TYPICAL UPPER-GATE DRIVE TURN-ON PATH
PVCC
D
C GD
its switching frequency to the fundamental frequency of the
input waveform. The maximum voltage to the FSYNC pin is
VCC + 0.3V. The Frequency Synchronization feature will
synchronize the leading edge of CLKOUT signal with the
falling edge of Channel 1’s PWM clock signal. The CLKOUT
is not available until the PLL locks.
The locking time is typically 130μs for F SW = 500kHz.
EN/VFF1 is released for a soft-start cycle until the FSYNC
R HI2
R LO2
LGATE
G
R G2
R GI2
C DS
stabilized and the PLL is in locking. The PLL circuits control
only EN/FF1, and control Channel 2’s soft-start instead of
EN/FF2. Therefore, it is recommended to connect all EN/FF
GND
C GS
S
Q2
pins together in multiphase configuration.
The loss of a synchronization signal for 13 clock cycles
causes the IC to be disabled until the PLL returns locking, at
FIGURE 20. TYPICAL LOWER-GATE DRIVE TURN-ON PATH
31
which point a soft-start cycle is initiated and normal
operation resumes. Holding FSYNC low will disable the IC.
March 20, 2009
FN6641.0
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