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| 型号： | ISL85402IRZ-TK |
| 厂商： | Intersil |
| 文件页数： | 13/22页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK BOOST SYNC ADJ 20QFN |
| 标准包装： | 1,000 |
| 类型： | 降压（降压），升压（升压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 3 V ~ 36 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz ~ 2.2MHz |
| 电流 - 输出： | 2.5A |
| 同步整流器： | 两者兼有 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 20-QFN（4x4） |
ISL85402
Functional Description
Initialization
Initially the ISL85402 continually monitors the voltage at the EN
pin. When the voltage on the EN pin exceeds its rising ON
default threshold is 700mA when there is no programming
resistor at the MODE pin.
The current threshold for PWM/PFM boundary can be
programmed by choosing the MODE pin resistor value calculated
from Equation 2, where IPFM is the desired PWM/PFM boundary
R MODE = ----------------------------------------
threshold, the internal LDO will start up to build up VCC. After
Power-On Reset (POR) circuits detect that VCC voltage has
exceeded the POR threshold, the soft-start will be initiated.
Soft-Start
The soft-start (SS) ramp is built up in the external capacitor on
the SS pin that is charged by an internal 5μA current source.
current threshold and R MODE is the programming resistor.
118500
IPFM + 0.2
500
400
(EQ. 2)
C SS [ μ F ] = 6.5 ? t SS [ S ]
(EQ. 1)
300
The SS ramp starts from 0 to a voltage above 0.8V. Once SS
reaches 0.8V, the bandgap reference takes over and IC gets into
steady state operation.
The SS plays a vital role in the hiccup mode of operation. The IC
works as cycle-by-cycle peak current limiting at over load
200
100
condition. When a harsh conditon occurs and the current in the
upper side MOSFET reaches the second overcurrent threshold,
the SS pin is pulled to ground and a dummy soft-start cycle is
initiated. At dummy SS cycle, the current to charge soft-start cap
0
0.0
0.2
0.4 0.6 0.8
I PFM (A)
FIGURE 25. R MODE vs I PFM
1.0
1.2
1.4
is cut down to 1/5 of its normal value. So a dummy SS cycle
takes 5x of the regular SS cycle. During the dummy SS period,
the control loop is disabled and no PWM output. At the end of
this cycle, it will start the normal SS. The hiccup mode persist
until the second overcurrent threshold is no longer reached.
The ISL85402 is capable of starting up with prebiased output.
PWM Control
Pulling the MODE pin to GND will set the IC in forced PWM mode.
The ISL85402 employs the peak current mode PWM control for
fast transient response and cycle-by-cycle current limiting. See
The PWM operation is initialized by the clock from the oscillator.
The upper MOSFET is turned on by the clock at the beginning of a
PWM cycle and the current in the MOSFET starts to ramp up.
When the sum of the current sense signal and the slope
compensation signal reaches the error amplifier output voltage
level, the PWM comparator is trigger to shut down the PWM logic
to turn off the high-side MOSFET. The high-side MOSFET stays off
until the next clock signal comes for next cycle.
The output voltage is sensed by a resistor divider from V OUT to
the FB pin. The difference between the FB voltage and 0.8V
reference is amplified and compensated to generate the error
voltage signal at the COMP pin. Then the COMP pin signal is
compared with the current ramp signal to shut down the PWM.
PFM Mode Operation
To pull the MODE pin HIGH (>2.5V) or leave the MODE pin floating
will set the IC to have PFM (Pulse Frequency Modulation)
operation in light load. In PFM mode, the switching frequency is
dramatically reduced to minimize the switching loss. The
ISL85402 enters PFM mode when the MOSFET peak current is
lower than the PWM/PFM boundary current threshold. The
13
Synchronous and Non-Synchronous Buck
The ISL85402 supports both Synchronous and non-synchronous
buck operations. For a non-synchronous buck operation when a
power diode is used as the low-side power device, the LGATE
driver can be disabled with LGATE connected to VCC (before IC
start-up).
AUXVCC Switch-Over
The ISL85402 has an auxiliary LDO integrated as shown in the
MAIN LDO function after the IC startup. “Typical Application
basic application setup with output voltage connected to
AUXVCC. After IC soft-start is done and the output voltage is built
up to steady state, and once the AUXVCC pin voltage is over the
AUX LDO Switch-over Rising Threshold, the MAIN LDO is shut off
and the AUXILIARY LDO is activated to bias VCC. Since the
AUXVCC pin voltage is lower than the input voltage V IN , the
internal LDO dropout voltage and the consequent power loss is
reduced. This feature brings substantial efficiency improvements
in light load range, especially at high input voltage applications.
When the voltage at AUXVCC falls below the AUX LDO Switch-over
Falling Threshold, the AUXILIARY LDO is shut off and the MAIN LDO
is re-activated to bias VCC. At the OV/UV fault events, the IC also
switches back over from AUXILIARY LDO to MAIN LDO.
The AUXVCC switchover function is offered in buck configuration.
It is not offered in boost configuration when the AUXVCC pin is
used to monitor the boost output voltage for OVP.
Input Voltage
With the part switching, the operating ISL85402 input voltage
must be under 36V. This recommendation allows for short
voltage ringing spikes (within a couple of ns time range) due to
FN7640.1
April 25, 2013
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