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参数资料
| 型号： | ISL85402IRZ-TK |
| 厂商： | Intersil |
| 文件页数： | 20/22页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK BOOST SYNC ADJ 20QFN |
| 标准包装： | 1,000 |
| 类型： | 降压（降压），升压（升压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 3 V ~ 36 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz ~ 2.2MHz |
| 电流 - 输出： | 2.5A |
| 同步整流器： | 两者兼有 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 20-QFN（4x4） |
ISL85402
Boost Output Capacitor
Based on the same theory in boost start-up previously described
in the boost inductor selection, a large capacitor at boost output
will cause high in-rush current at boost PWM start-up. 22μF is a
good choice for applications with a buck output voltage less than
10V. Also some minimum amount of capacitance has to be used
in boost output to keep the system stable. It is suggested to run
the iSim model, which is available on the internet to assist in
designing the proper capacitor value.
Layout Suggestions
1. Place the input ceramic capacitors as closely as possible to
the IC VIN pin and power ground connecting to the power
MOSFET or Diode. Keep this loop (input ceramic capacitor, IC
VIN pin and MOSFET/Diode) as tiny as possible to achieve the
least voltage spikes induced by the trace parasitic
inductance.
2. Place the input aluminum capacitors closely as possible to
the IC VIN pin.
3. Keep the phase node copper area small but large enough to
handle the load current.
4. Place the output ceramic and aluminum capacitors close to
the power stage components as well.
5. Place vias ( ≥ 9) in the bottom pad of the IC. The bottom pad
should be placed in ground copper plane with an area as large
20
as possible in multiple layers to effectively reduce the thermal
impedance.
6. Place the 4.7μF ceramic decoupling capacitor at the VCC pin
(the closest place to the IC). Put multiple vias ( ≥ 3) close to the
ground pad of this capacitor.
7. Keep the bootstrap capacitor close to the IC.
8. Keep the LGATE drive trace as short as possible and try to
avoid using via in the LGATE drive path to achieve the lowest
impedance.
9. Place the positive voltage sense trace close to the place to be
strictly regulated.
10. Place all the peripheral control components close to the IC.
FIGURE 32. PCB VIA PATTERN
FN7640.1
April 25, 2013
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