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参数资料
| 型号： | ISL85402IRZ-TK |
| 厂商： | Intersil |
| 文件页数： | 2/22页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK BOOST SYNC ADJ 20QFN |
| 标准包装： | 1,000 |
| 类型： | 降压（降压），升压（升压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 可调至 0.8V |
| 输入电压： | 3 V ~ 36 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 200kHz ~ 2.2MHz |
| 电流 - 输出： | 2.5A |
| 同步整流器： | 两者兼有 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 20-QFN（4x4） |
ISL85402
Pin Configuration
ISL85402
(20 LD QFN)
TOP VIEW
EN
FS
1
2
20
19
18
17
16
15
14
BOOT
PGND
21
SS
FB
COMP
3
4
5
Thermal Pad
21
PAD
13
12
11
LGATE
SYNC
EXT_BOOST
6
7
8
9
10
Functional Pin Descriptions
PIN NAME
EN
FS
SS
FB
COMP
ILIMIT
MODE
PGOOD
PHASE
EXT_BOOST
PIN #
1
2
3
4
5
6
7
8
9, 10
11
DESCRIPTION
The controller is enabled when this pin is left floating or pulled HIGH. The IC is disabled when this pin is pulled LOW.
Range: 0V to 5.5V.
Connecting this pin to VCC, or GND, or leaving it open will force the IC to have 500kHz switching frequency. The oscillator
switching frequency can also be programmed by adjusting the resistor from this pin to GND.
Connect a capacitor from this pin to ground. This capacitor, along with an internal 5μA current source, sets the soft-start
interval of the converter. Also, this pin can be used to track a ramp on this pin.
This pin is the inverting input of the voltage feedback error amplifier. With a properly selected resistor divider connected from
V OUT to FB, the output voltage can be set to any voltage between the power rail (reduced by maximum duty cycle and voltage
drop) and the 0.8V reference. Loop compensation is achieved by connecting an RC network across COMP and FB. The FB pin
is also monitored for overvoltage events.
Output of the voltage feedback error amplifier.
Programmable current limit pin. With this pin connected to the VCC pin, or to GND, or left open, the current limiting threshold
is set to default of 3.6A; the current limiting threshold can be programmed with a resistor from this pin to GND.
Mode selection pin. Pull this pin to GND for forced PWM mode; to have it floating or connected to VCC will enable PFM mode
when the peak inductor current is below the default threshold of 700mA. The current boundary threshold between PFM and
PWM can also be programmed with a resistor at this pin to ground. Check for more details in the “PFM Mode Operation” on
PGOOD is an open drain output that will be pulled low immediately under the events when the output is out of regulation (OV
or UV) or when the EN pin is pulled low. PGOOD is equipped with a fixed delay of 1000 cycles upon output power-up (V O > 90%).
These pins are the PHASE nodes that should be connected to the output inductor. These pins are connected to the source of
the high-side N-channel MOSFET.
This pin is used to set boost mode and monitor the battery voltage that is the input of the boost converter. After VCC POR, the
controller will detect the voltage on this pin; if voltage on this pin is below 200mV, the controller is set in
synchronous/non-synchronous buck mode and will latch in this state unless VCC is below POR falling threshold; if the voltage
on this pin after VCC POR is above 200mV, the controller is set in boost mode and latch in this state. In boost mode, the
low-side driver output PWM with same duty cycle with upper-side driver to drive the boost switch.
In boost mode, this pin is used to monitor input voltage through a resistor divider. By setting the resistor divider, the high
threshold and hysteresis can be programmed. When voltage on this pin is above 0.8V, the PWM output (LGATE) for the boost
converter is disabled, and when voltage on this pin is below 0.8V minus the hysteresis, the boost PWM is enabled.
In boost mode operation, PFM is disabled when boost PWM is enabled. Check the “Boost Converter Operation” on page 14
for more details.
2
FN7640.1
April 25, 2013
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