参数资料
型号: ISL9506HRZ-T
厂商: Intersil
文件页数: 16/27页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 40-QFN
标准包装: 4,000
系列: Robust Ripple Regulator™ (R³)
PWM 型: 控制器
输出数: 1
频率 - 最大: 500kHz
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -10°C ~ 100°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL9506
Theory of Operation
Operational Description
V DD
The ISL9506 is a multiphase regulator for digital processor
core power application. It can be programmed for 1-, 2- or 3-
VR_EN
10mV/μs
2mV/μs
channel operation. With ISL6208 gate driver capable of
diode emulation, the ISL9506 provides optimum efficiency in
120μs
1.2V
90%
VSEL COMMANDED
VOLTAGE
both heavy and light load conditions.
ISL9506 uses Intersil patented R 3 (Robust Ripple
Regulator?) modulator. The R 3 ? modulator combines the
best features of fixed frequency PWM and hysteretic PWM
while eliminating many of their shortcomings. The ISL9506
modulator internally synthesizes analog signals inside the IC
SOFT & VO
PGD_N
13 SWITCHING CYCLES
emulating the inductor ripple currents and use hysteretic
comparators on those signals to determine switching pulse
PGOOD
~7ms
widths. Operating on these large-amplitude, noise-free
synthesized signals allows the ISL9506 to achieve lower
output ripple and lower phase jitter than conventional
hysteretic and fixed PWM mode controllers. Unlike
conventional hysteretic converters, the ISL9506 has an error
amplifier that allows the controller to maintain a 0.5% output
voltage accuracy. At heavy load conditions, the ISL9506 is
switching at a relatively constant switching frequency similar
to fixed frequency PWM controller. At light load conditions,
the ISL9506 is switching at a frequency proportional to load
current similar to hysteretic mode controller.
The hysteresis window voltage rides on the error amplifier
output such that a load current transient results in an
increase in switching frequency to give the R 3 regulator a
faster response than conventional fixed frequency PWM
FIGURE 42. SOFT-START WAVEFORMS USING A 20nF SOFT
CAPACITOR
the soft-start sequence starting 120μs after V DD crosses the
POR threshold.
Static Operation
VOLTAGE REGULATION AT ZERO LOAD CURRENT
After the start sequence, the output voltage will be regulated
to the value set by the VSEL inputs per Table 1. The ISL9506
will control the no-load output voltage to an accuracy of ±0.5%
over the range of 0.75V to 1.5V.
TABLE 1. VOLTAGE SELECTION TABLE
VSEL5 VSEL4 VSEL3 VSEL2 VSEL1 VSEL0 VSEL6=0 VSEL6=1
controllers. The sharing of the hysteretic window voltage
also inherently shares the transient load current between the
phases. The individual average phase voltages are
monitored and controlled to equally share the static current
among the phases.
The ISL9506 disables PWM2 when LP is asserted low, and
the power monitor pin provides an analog signal
representing the output power of the converter.
Start-up Timing
With the controller's +5V V DD voltage above the POR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1.5000
1.4875
1.4750
1.4625
1.4500
1.4375
1.4250
1.4125
1.4000
0.7000
0.6875
0.6750
0.6625
0.6500
0.6375
0.6250
0.6125
0.6000
threshold, the start-up sequence begins when VR_EN
exceeds the 3.3V logic HIGH threshold. Approximately
120μs later SOFT and V OUT start ramping up to the start
voltage of 1.2V. During this interval, the SOFT capacitor is
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
0
1
1.3875
1.3750
1.3625
0.5875
0.5750
0.5625
charged with approximately 40μA. Therefore, if the SOFT
capacitor is selected to be 20nF, the SOFT ramp will be at
about 2mV/μs for a soft-start time of 600μs. Once V OUT is
within 10% of the start voltage for 13 PWM cycles (43μs for
0
0
0
0
0
0
1
1
1
1
1
1
0
0
1
0
1
0
1.3500
1.3375
1.3250
0.5500
0.5375
0.5250
frequency = 300kHz), then PGD_N is pulled LOW and the
SOFT capacitor is charged up with approximately 200μA.
Therefore, V OUT slews at +10mV/μs to the voltage set by
the VSEL pins. Approximately 7ms later, PGOOD is
asserted HIGH. A typical start-up timing is shown in
Figure 42. Similar results occur if VR_EN is tied to V DD , with
0
0
0
0
0
1
1
1
1
0
0
0
1
0
0
0
1
0
0
1
1
0
1
0
1.3125
1.3000
1.2875
1.2750
0.5125
0.5000
0.4875
0.4750
16
FN6722.0
August 13, 2008
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