参数资料
型号: ISL9506HRZ-T
厂商: Intersil
文件页数: 24/27页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 40-QFN
标准包装: 4,000
系列: Robust Ripple Regulator™ (R³)
PWM 型: 控制器
输出数: 1
频率 - 最大: 500kHz
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -10°C ~ 100°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL9506
DCR = 0.0012 Ω typical, Rdrp1 = 1k Ω and the attenuation
gain (G1) = 0.57, Rdrp2 is then:
Dynamic Mode of Operation - Dynamic Droop
using DCR Sensing
Rdrp2 = ? ------------------------------------ – 1 ? × 1K = 8.21k Ω
3 × 0.0021
? 0.0012 × 0.57 ?
(EQ. 16)
Droop is very important for load transient performance. If the
system is not compensated correctly, the output voltage
L ? Rn × RS EQV ?
? Rn + RS EQV ?
Rdrp2 is selected to be a 8.25k_1% resistor. Note, we
choose to ignore the RO resistors because they do not add
significant error.
These values are extremely sensitive to layout and coupling
factor of the NTC to the inductor. As only one NTC is
required in this application, this NTC should be placed as
close to the Channel 1 inductor as possible. And very
importantly, the PCB traces sensing the inductor voltage
should be go directly to the inductor pads.
could sag excessively upon load application and potentially
create a system failure. The output voltage could also take a
long period of time to settle to its final value.
The L/DCR time constant of the inductor must be matched to
the Rn*Cn time constant as shown in Equation 18:
------------- = ? ----------------------------------- ? × Cn (EQ. 18)
DCR
Solving for Cn we now have Equation 19:
L
Cn = -----------------------------------------
? Rn × RS EQV ?
Once the board has been laid out, some adjustments may
be required to adjust the full load droop voltage. This can be
accomplished by allowing the system to achieve thermal
equilibrium at full load, and then adjusting Rdrp2 to obtain
-------------
DCR
? ----------------------------------- ?
? Rn + RS EQV ?
(EQ. 19)
0.5 μ H
(EQ. 20)
Cn = ------------------------------------------------- = 28.5nF
? ------------------------------------------- ?
the appropriate droop impedance.
To see whether the NTC has compensated the temperature
change of the DCR, the user can apply full load current and
wait for the thermal steady state and see how much the
output voltage will deviate from the initial voltage reading. A
good NTC thermistor compensation can limit the output
voltage drift to 2mV. If the output voltage is decreasing with
temperature increase, that ratio between the NTC thermistor
value and the rest of the resistor divider network has to be
increased. Users should use the ISL9506 evaluation board
component values and follow the evaluation board layout of
NTC as much as possible to minimize engineering time.
The desired droop impedance should be adjusted by Rdrp2
based on maximum current steps, not based on small current
steps. Basically, if the max current is 40A, the required droop
voltage is 84mV with 2.1m Ω droop impedance. The user
should have 40A load current on the converter and look for
84mV droop. If the droop voltage is less than 84mV, for
example, 80mV. The new value will be calculated by
Equation 17:
Note, RO was neglected. As long as the inductor time
constant matches the droop circuit RC time constants as
given above, the transient performance will be optimum. The
selection of Cn may require a slight adjustment to correct for
layout inconsistencies and component tolerance. For the
example of L = 0.5 μ H, Cn is calculated in Equation 20:
------------------
0.0012
3.4k Ω × 2.56k Ω
? 3.4k Ω + 2.56k Ω ?
The value of this capacitor is selected to be 27nF. As the
inductors tend to have 20% to 30% tolerances, this cap
generally will be tuned on the board by examining the
transient voltage. If the output voltage transient has an initial
dip, lower than the voltage required by the droop impedance,
and is slowly increasing back to the steady state, the
capacitor should be increased and vice versa. It is better to
have the capacitor value a little bigger to cover the tolerance
of the inductor to prevent the output voltage from going lower
than the spec. This capacitor needs to be a high grade
capacitor like X7R with low tolerance. There is another
Rdrp 2 _ new
=
84 mV
80 mV
( Rdrp 1 + Rdrp 2 ) ? Rdrp 1
(EQ. 17)
consideration in order to achieve better time constant match
mentioned above. The NPO/COG (class-I) capacitors have
only 5% tolerance and a very good thermal characteristics.
For the best accuracy, the equivalent resistance on the DFB
and VSUM pins should be identical so that the bias current
of the droop amplifier does not cause an offset voltage. In
the example above, the resistance on the DFB pin is Rdrp1
in parallel with Rdrop2, that is, 1k in parallel with 8.21k or
890 Ω . The resistance on the VSUM pin is Rn in parallel with
RSeqv or 3.4k in parallel with 2.56k or 1460 Ω . The mismatch
in the effective resistances is 1460 - 890 = 570 Ω . To reduce
the mismatch, multiply both Rdrp1 and Rdrp2 by the
appropriate factor. The appropriate factor in the example is
1460/890 = 1.64.
24
But those capacitors are only available in small capacitance
values. In order to use such capacitors, the resistors and
thermistors surrounding the droop voltage sensing and
droop amplifier has to be resized up to 10x to reduce the
capacitance by 10x. But attention has to be paid in balancing
the impedance of droop amplifier in this case.
Dynamic Mode of Operation - Compensation
Parameters
Considering the voltage regulator as a black box with a
voltage source controlled by VSEL and a series impedance,
in order to achieve certain droop impedance, the series
impedance inside the black box needs to be this desired
FN6722.0
August 13, 2008
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