参数资料
型号: ISL9506HRZ-T
厂商: Intersil
文件页数: 25/27页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 40-QFN
标准包装: 4,000
系列: Robust Ripple Regulator™ (R³)
PWM 型: 控制器
输出数: 1
频率 - 最大: 500kHz
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -10°C ~ 100°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL9506
value. The compensation design has to ensure the output
impedance of the converter be lower than this desired value.
There is a mathematical calculation file available to the user.
The power stage parameters such as L and Cs are needed
as the input to calculate the compensation component
values. Attention has be paid to the input resistor to the FB
pin. Too high of a resistor will cause an error to the output
voltage regulation because of bias current flowing in the FB
pin. It is better to keep this resistor below 3k when using this
file.
Static Mode of Operation - Current Balance using
DCR or Discrete Resistor Current Sensing
Current Balance is achieved in the ISL9506 through the
matching of the voltages present on the ISEN pins. The
ISL9506 adjusts the duty cycles of each phase to maintain
equal potentials on the ISEN pins. RL and CL around each
inductor, or around each discrete current resistor, are used
to create a rather large time constant such that the ISEN
voltages have minimal ripple voltage and represent the DC
current flowing through each channel’s inductor. For
optimum performance, RL is chosen to be 10k Ω and CL is
selected to be 0.22μF. When discrete resistor sensing is
used, a capacitor of 10nF should be placed in parallel with
RL to properly compensate the current balance circuit.
1. ISL9506 uses RC filter to sense the average voltage on
phase node and forces the average voltage on the phase
node to be equal for current balance. Even though the
ISL9506 forces the ISEN voltages to be almost equal, the
inductor currents will not be exactly the same. Take DCR
current sensing as example, two errors have to be added
to find the total current imbalance. 1) Mismatch of DCR:
If the DCR has a 5% tolerance, then the resistors could
mismatch by 10% worst case. If each phase is carrying
20A then the phase currents mismatch by
20A*10% = 2A. 2) Mismatch of phase voltages/offset
voltage of ISEN pins. The phase voltages are within 2mV
of each other by current balance circuit. The error current
that results is given by 2mV/DCR. If DCR = 1m Ω then the
error is 2A.
In the above example, the two errors add to 4A. For a two
phase DC/DC, the currents would be 22A in one phase and
18A in the other phase. In the above analysis, the current
balance can be calculated with 2A/20A = 10%. This is the
worst case calculation, for example, the actual tolerance of
two 10% DCRs is 10%*sqrt(2) = 7%.
There are provisions to correct the current imbalance due to
layout or to purposely divert current to certain phase for better
thermal management. Customer can put a resistor in parallel
with the current sensing capacitor on the phase of interest in
much trace resistance a resistor can be added in parallel
with the ISEN capacitor that will correct for the poor layout.
An estimate of the value of the resistor is:
Rtweak = Risen* [2*Rdcr - (Rtrace - Rmin)]/[2(Rtrace - Rmin)]
(EQ. 21)
where Risen is the resistance from the phase node to the
ISEN pin; usually 10k Ω . Rdcr is the DCR resistance of the
inductor. Rtrace is the trace resistance from the inductor to
the point of load on the phase that needs to be tweaked. It
should be measured with a good micro Ω meter. R MIN is the
trace resistance from the inductor to the load on the phase
with the least resistance.
For example, if the PC board trace on one phase is 0.5m Ω
and on another trace is 0.3m Ω ; and if the DCR is 1.2m Ω ;
then the tweaking resistor is
Rtweak = 10kw* [2*1.2 - (0.5 - 0.3)]/[2*(0.5 - 0.3)] = 55k Ω (EQ. 22)
For extremely unsymmetrical layout causing phase current
unbalance, ISL9506 applications schematics can be
modified to correct the problem.
Droop using Discrete Resistor Sensing - Static/
Dynamic Mode of Operation
When choosing current sense resistor, not only the tolerance
of the resistance is important, but also the TCR. Thus, its
combined tolerance at a wide temperature range should be
calculated.
Figure 48 shows the equivalent circuit of a discrete current
sense approach. Figure 40 shows the simplified schematic
of this approach.
For discrete resistor current sensing circuit, the droop circuit
parameters can be solved the same way as the DCR
sensing approach with a few slight modifications.
First, there is no NTC required for thermal compensation,
therefore, the Rn resistor network in the previous section is
not required. Secondly, there is no time constant matching
required, therefore, the Cn component is not needed to
match the L/DCR time constant, but this component does
indeed provide noise immunity, especially to noise voltage
caused by the ESL of the current sensing resistors. A 47pF
capacitor can be used for such purposes.
The Rs values in the previous section, Rs = 7.68k_1% are
sufficient for this approach.
Now, the input to the Droop amplifier is the V RSENSE
voltage. This voltage is given by Equation 23:
Vrsense = -------------------- × I OUT
order to purposely increase the current in that phase. It is
highly recommended to use symmetrical layout in order to
Rsense
N
(EQ. 23)
achieve natural current balance.
In the case the PCB board trace resistance from the inductor
The gain of the Droop amplifier, G2, must be adjusted equal
to the droop impedance. See Equation 24:
G2 = ---------------------- × N
to the point of load are not the same on all three phases, the
current will not be balanced. On the phases that have too
25
Rdroop
Rsense
(EQ. 24)
FN6722.0
August 13, 2008
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