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参数资料
| 型号： | ISL9506HRZ-T |
| 厂商： | Intersil |
| 文件页数： | 19/27页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 40-QFN |
| 标准包装： | 4,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 500kHz |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -10°C ~ 100°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ISL9506
TABLE 3. THE FAULT PROTECTION AND RESET OPERATION OF ISL9506
FAULT DURATION
PRIOR TO
PROTECTION
PROTECTION
ACTIONS
FAULT RESET
Overcurrent
Way-Overcurrent (2.5 X
120μs
<2μs
PWMs tri-state, PGOOD latched low
PWMs tri-state, PGOOD latched low
VR_EN toggle or VDD toggle
VR_EN toggle or VDD toggle
OC)
Overvoltage 1.7V
Immediately
Low side MOSFET on until Vcore <0.85V, then PWM
VDD toggle
tri-state, PGOOD latched low.
Overvoltage +200mV
Undervoltage -300mV
Phase-Current Unbalance
Over-Temperature
1ms
1ms
1ms
Immediately
PWMs tri-state, PGOOD latched low
PWMs tri-state, PGOOD latched low
PWMs tri-state, PGOOD latched low
VRHOT# goes low
VR_EN toggle or VDD toggle
VR_EN toggle or VDD toggle
VR_EN toggle or VDD toggle
N/A
Protection
The ISL9506 provides overcurrent, overvoltage, and
undervoltage protection. Overcurrent protection is related to
the voltage droop which is determined by the droop
impedance requirement. After the load-line is set, the OCSET
resistor can be selected to detect overcurrent at any level of
droop voltage. For overcurrent less that 2.5x the OCSET
level, the overload condition must exist for 120μs in order to
trip the OC fault latch. This is shown in Figure 28.
For overload exceeding 2.5x the OCSET level, the PWM
outputs will immediately shut off and PGOOD will go low to
maximize protection due to hard short circuit. This protection
was referred to as way-overcurrent or fast over current, for
short-circuit protections.
In addition, excessive phase unbalance due to gate driver
failure will be detected and will shut down the controller. The
phase unbalance is detected by the voltage on the ISEN pin.
If the ISEN pin voltage difference is greater than 9mV for 1ms,
the controller will latch off.
Undervoltage protection is independent of the overcurrent
limit. If the output voltage is less than the VSEL set value by
300mV or more, a fault will latch after 1ms in that condition.
The PWM outputs will turn off and PGOOD will go low. This
is shown in Figure 27. Note that most practical core voltage
regulators will have the overcurrent set to trip before the
-300mV undervoltage limit.
There are two levels of overvoltage protection with different
responses. The first level of overvoltage protection is
referred to as PGOOD overvoltage protection. Basically, for
these inputs are returned to their high operating levels, a
soft-start will occur.
The second level of overvoltage protection behaves
differently. If the output exceeds 1.7V, an OV fault is
immediately declared, PGOOD is latched low and the
low-side FETs are turned on. The low-side FETs will remain
on until the output voltage is pulled down below 0.85V at
which time all FETs are turned off. If the output again rises
above 1.7V, the process is repeated. This affords the
maximum amount of protection against a shorted high-side
FET while preventing output ringing below ground. The 1.7V
OVP cannot be reset with VR_EN, but requires that V DD be
lowered to reset. The 1.7V OV detector is nominal at all
times when the controller is enabled including after one of
the other faults occurs. This ensures the load is protected
against high-side FET leakage while the FETs are
commanded off. The ISL9506 has a thermal throttling
feature. If the voltage on the NTC pin goes below the 1.18V
OT threshold, the VRHOT# pin is pulled low indicating the
need for thermal throttling to the system oversight load. No
other action is taken within the ISL9506 in response to NTC
pin voltage.
Fault protection is summarized in Table 3.
Power Monitor
The power monitor signal is an analog output. Its magnitude
is proportional to the product of VSEN and the voltage
difference between V DROOP and V O , which is the
programmed droop impedance multiplied by load current.
The output voltage of the PMON pin is given by:
output voltage exceeding the set value by +200mV for 1ms,
a fault will be declared with PGOOD latched low.
V PMON = V SEN * (V
DROOP
– V O ) *17.5 (Volt)
(EQ. 1)
All of the above faults have the same action taken: PGOOD
The power consumed by the load can be calculated by:
is latched low and the upper and lower power FETs are
turned off so that inductor current will decay through the
FETbody diodes. This condition can be reset by bringing
P LOAD = V PMON /(17.5*0.0021) (Watt)
(EQ. 2)
VR_EN low or by bringing V DD below POR threshold. When
19
where the 0.0021 is the droop impedance.The power
monitor load regulation is about 7 Ω . Basically, within its
FN6722.0
August 13, 2008
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