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参数资料
| 型号： | ISL9506HRZ-T |
| 厂商： | Intersil |
| 文件页数： | 18/27页 |
| 文件大小： | 0K |
| 描述： | IC REG CTRLR BUCK PWM 40-QFN |
| 标准包装： | 4,000 |
| 系列： | Robust Ripple Regulator™ (R³) |
| PWM 型： | 控制器 |
| 输出数： | 1 |
| 频率 - 最大： | 500kHz |
| 电源电压： | 4.75 V ~ 5.25 V |
| 降压： | 是 |
| 升压： | 无 |
| 回扫： | 无 |
| 反相： | 无 |
| 倍增器： | 无 |
| 除法器： | 无 |
| Cuk： | 无 |
| 隔离： | 无 |
| 工作温度： | -10°C ~ 100°C |
| 封装/外壳： | 40-VFQFN 裸露焊盘 |
| 包装： | 带卷 (TR) |
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ISL9506
SWITCHING FREQUENCY IN CCM/DCM MODE
The switching frequency is adjusted by the resistor between
the error amplifier output and the VW pin. When ISL9506 is
in continuous conduction mode (CCM), the switching
frequency may not be as constant as that of a fixed
frequency PWM controllers. However, the switching
frequency variation will be kept small to maintain the output
voltage ripple within specification. In general, the switching
frequency will be very close to the set value at high input
voltage and heavy load conditions.
The hysteresis window voltage is constructed with a resistor on
the VW pin to the error amplifier outputs. The synthesized
inductor current ripple signal compares with the window voltage
and generates PWM signal. At load current step-up, the
switching frequency is increased resulting in a faster response
than conventional fixed frequency PWM controllers. As all the
phases shares the same hysteretic window voltage, it also
ensures excellent dynamic current balance between phases.
The individual average phase voltages are monitored and
controlled to achieve steady state current balance among the
phases with current balance loop.
When DE_EN is high and DE_ENN is low, the FCCM pin will
become low, and discontinuous conduction mode (DCM)
operation will be allowed in the ISL6208 gate drive. In DCM,
ISL6208 turns off the lower FET after its channel current
across zero. As load is further reduced, channel switching
frequency will drop, providing optimized efficiency at light
load. FCCM logic low is the signal to enable, or to allow the
DCM operation. Only if the inductor current is really cross
zero, does the true DCM occur.
VOUT
Modes of Operation Programmed by Logic Signals
The operational modes of ISL9506 are programmed by the
control signals of DE_EN, DE_ENN, and LP. ISL9506
responds LP signal by adding or dropping PWM2 and
adjusting the overcurrent protection level accordingly. For
example, if the ISL9506 is initially used as 3-phase
controller, the LP signal will add or drop PWM2 and leave
PWM1 and PWM3 always in operation. Meanwhile, after
PWM2 is dropped, the phase shift between the PWM1 and
DE_ENN
DE_EN
VSEL6
-2m V/μS
2m V/μS
10m V/μS
PWM3 is adjusted from 120° to 180° and the overcurrent
and the way-overcurrent protection level will be adjusted to
2/3 of the initial value. If the ISL9506 is initially used as
2-phase operation, it is suggested that PWM1 and PWM2
pair, not PWM1 and PWM3 pair, should be used such that
the LP signal will enable or disable PWM2 with PWM1 in
operation always. The overcurrent and way-overcurrent
protection level in two-to-one phase mode operation will be
adjusted as two-to-one as well.
The DCM mode operation is independent of LP for ISL9506.
FIGURE 43. DIODE EMULATION TRANSITION SHOWING
DE_EN’s EFFECT ON EXIT SLEW RATE
Dynamic Operation
Refer to Figure 43. The ISL9506 responds to changes in
VSEL command voltage by slewing to new voltages with a
dV/dt set by the SOFT capacitor and by the state of DE_EN.
With C SOFT = 20nF and DE_EN is HIGH, the output voltage
will move at ±2mV/μs for large changes in voltage. For
It responds to the DE_EN and DE_ENN. Table 2 shows the
operation modes of ISL9506 with combinations of control
logic.
When LP is de-asserted low, ISEN2 pin is connected to the
ISEN pins of the operational phases internally to keep
proper current balance and minimize the inductor current
overshoot and undershoot when the disabled phase is
enabled again.
DE_EN LOW, the large signal dV/dt will be ±10mV/μs. As
the output approaches the VSEL command voltage, the
dV/dt rate moderates to prevent overshoot. During
Geyserville III transitions where there is one LSB VSEL step
each 5μs, the controller will follow the VSEL command with
DE_EN
0
TABLE 2. ISL9506 MODE OF OPERATIONS
MODE OF
DE_ENN LP OPERATION MODE
1 1 N phase CCM Nominal
its dV/dt rate of ±2.5mV/μs.
Keeping DE_EN HIGH during VSEL transitions will result in
reduced dV/dt slew rate and lesser audio noise. For fastest
recovery from Diode Emulation to Nominal mode, DE_EN
LOW achieves higher dV/dt.
Intersil's R 3 intrinsically has voltage-feed-forward. The
output voltage is insensitive to a fast slew input voltage
0
1
1
0
0
1
1
1
0
0
0
0
1
1
0
1
0
1
0
1
0
N-1 phase CCM
N phase DCM
N-1 phase DCM
N phase CCM
N-1 phase CCM
N phase CCM
N-1phase CCM
Low Power
Diode
Emulation
Diode
Emulation
Transient Performance.
18
FN6722.0
August 13, 2008
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