参数资料
型号: ISL9506HRZ-T
厂商: Intersil
文件页数: 3/27页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 40-QFN
标准包装: 4,000
系列: Robust Ripple Regulator™ (R³)
PWM 型: 控制器
输出数: 1
频率 - 最大: 500kHz
电源电压: 4.75 V ~ 5.25 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -10°C ~ 100°C
封装/外壳: 40-VFQFN 裸露焊盘
包装: 带卷 (TR)
ISL9506
PWM2 (Pin 26)
PWM output for Channel 2. For ISL9506, LP low will make
this output tri-state. When PWM2 is pulled to 5V VDD,
PWM2 will be disabled and allow other channels to operate.
PWM1 (Pin 27)
PWM output for channel 1.
VSEL0:6 (Pin28:Pin34)
Voltage Selection input with VSEL0 = LSB and VSEL6
= MSB.
VR_EN (Pin 35)
Voltage Regulator Enable input. A high level logic signal on
this pin enables the regulator.
DE_EN (Pin 36)
Diode Emulation Enable signal. A high level logic signal on
this pin will allow diode emulation operation. Only if the
current is low enough, the diode emulation will actually be
entered. DE_EN logic high also affects the output voltage
transition from one voltage selection to anther programmed
by voltage select.
3
DE_ENN (Pin 37)
DE_EN and DE_ENN work together for diode emulation.
Generally a reversed logic signal of DE_EN should be
applied to DE_ENN.
PGD_N (Pin 38)
Digital output prior to PGOOD high. Goes nominal (logic 0)
after 13 switching cycles after V OUT is within 10% of 1.2V
voltage at start-up.
3V3 (Pin 39)
3.3V supply voltage for PGD_N logic, such an
implementation will increase power consumption from 3.3V
compared to open drain circuit other wise.
PGOOD (Pin 40)
Power Good open-drain output. Will be pulled up externally
by a 1.9k Ω resistor to 3.3V.
FN6722.0
August 13, 2008
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