参数资料
型号: ISL95874IRUZ-T
厂商: Intersil
文件页数: 19/29页
文件大小: 0K
描述: IC CTRLR PWM 1PHASE GPU 16UTQFN
标准包装: 3,000
应用: 控制器,GPU 内核电源
输入电压: 3.3 V ~ 25 V
输出数: 1
输出电压: 0.5 V ~ 5 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 16-UFQFN 裸露焊盘
供应商设备封装: 16-UTQFN(2.6x1.8)
包装: 带卷 (TR)
ISL95874, ISL95875, ISL95876
V OUT
R FB
FB
?
+
EA
V COMP
removing all setpoint programming resistors, connecting the
SET0 pin to the VCC pin, and feeding the external setpoint
reference voltage to the VID0 pin. When SET0 and VCC are tied
together, the following internal reconfigurations take place:
+
V SET
?
V REF
0.5V
- VID0 pin opens its 500nA pull-down current sink
- An internal switch changes position from the internal
reference source of 500mV to the VID0 pin and accepts an
external reference.
- VID1 pin is disabled
SREF
SET0
SET1
SET2
SW0
SW1
SW2
SW3
The converters will now be in regulation when the voltage on the
FB pin equals the voltage on the VID0 pin. As with
resistor-programmed setpoints, the reference voltage range on
the VID0 pin is 500mV to 1.5V. Use Equation 8 should it become
necessary to implement an output voltage-divider network to
make the external setpoint reference voltage compatible with
the 500mV to 1.5V constraint.
R 4 Modulator
The R 4 modulator is an evolutionary step in R 3 technology. Like
R 3 , the R 4 modulator allows variable frequency in response to
load transients and maintains the benefits of current-mode
hysteretic controllers. However, in addition, the R 4 modulator
reduces regulator output impedance and uses accurate
FIGURE 12. ISL95876 VOLTAGE PROGRAMMING CIRCUIT
If the output voltage is in the range of 0.5V to 1.5V, the external
resistor-divider is not necessary. The output voltage is equal to
one of the reference voltages depending on the status of VID1
and VID0. The external resistor divider consisting of R FB and
R OFS allows the user to program the output voltage in the range
of 1.5V to 5V. The relation between the output voltage and the
reference is given in Equation 30:
referencing to eliminate the need for a high-gain voltage
amplifier in the compensation loop. The result is a topology that
can be tuned to voltage-mode hysteretic transient speed while
maintaining a linear control model and removes the need for any
compensation. This greatly simplifies the regulator design for
customers and reduces external component cost.
Stability
The removal of compensation derives from the R 4 modulator’s
V OUT = V SREF ? ------------------------------ = V SREF ? k
R FB + R OFS
R OFS
(EQ. 30)
lack of need for high DC gain. In traditional architectures, high DC
gain is achieved with an integrator in the voltage loop. The
integrator introduces a pole in the open-loop transfer function at
V OUTx = V SETx ? k
In this case, the four output voltages are equal to each of the
corresponding reference voltages multiplying the factor k.
(EQ. 31)
High Output Voltage Programming
The ISL95874 has a fixed 0.5V reference voltage (V SREF ). For high
output voltage applications, the resistor divider consisting of R FB
and R OFS requires a large ratio (R FB :R OFS = 9:1 for 5V output). The
FB pin with large ratio resistor divider is noise sensitive and the PCB
layout should be carefully routed. It is recommended to use small
value resistor divider such as R FB = 1k Ω.
low frequencies. Thus, when combined with the double-pole from
the output L/C filter, creates a three pole system that must be
compensated to maintain stability.
Classic control theory requires a single-pole transition through
unity gain to ensure a stable system. Current-mode architectures
(includes peak, peak-valley, current-mode hysteretic, R 3 and R 4 )
generate a zero at or near the L/C resonant point, effectively
canceling one of the system’s poles. The system still contains
two poles, one of which must be canceled with a zero before
unity gain crossover to achieve stability. Compensation
components are added to introduce the necessary zero.
In general, the ISL95875 and ISL95876 have much better jitter
performance than the ISL95874 when the output voltage is in
the range of 3.3V to 5V, particularly in DCM. This is because
COMPENSATION TO COUNTER
INTEGRATOR POLE
INTEGRATOR
FOR HIGH DC GAIN
V SREF voltage can be set to 1.5V and a smaller ratio resistor
divider can be used. This makes the signal-to-noise ratio at FB pin
much better. So for 3.3V to 5V output, the ISL95875 and
ISL95876 are recommended with V SREF set to 1.5V.
External Setpoint Reference
The ISL95875 and ISL95876 can use an external setpoint
reference voltage as an alternative to VID-selected,
resistor-programmed setpoints. This is accomplished by
19
V OUT
V COMP
V DAC
FIGURE 13. INTEGRATOR ERROR-AMPLIFIER CONFIGURATION
FN7933.1
March 2, 2012
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