参数资料
型号: ISL95874IRUZ-T
厂商: Intersil
文件页数: 24/29页
文件大小: 0K
描述: IC CTRLR PWM 1PHASE GPU 16UTQFN
标准包装: 3,000
应用: 控制器,GPU 内核电源
输入电压: 3.3 V ~ 25 V
输出数: 1
输出电压: 0.5 V ~ 5 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 16-UFQFN 裸露焊盘
供应商设备封装: 16-UTQFN(2.6x1.8)
包装: 带卷 (TR)
ISL95874, ISL95875, ISL95876
Where:
- Q GATE is the amount of gate charge required to fully charge
the gate of the upper MOSFET
- Δ V BOOT is the maximum decay across the BOOT capacitor
As an example, suppose the high-side MOSFET has a total gate
charge Q g , of 25nC at V GS = 5V, and a Δ V BOOT of 200mV. The
calculated bootstrap capacitance is 0.125μF; for a comfortable
margin, select a capacitor that is double the calculated
capacitance. In this example, 0.22μF will suffice. Use a low
temperature-coefficient ceramic capacitor.
Driver Power Dissipation
Switching power dissipation in the driver is mainly a function of
the switching frequency and total gate charge of the selected
MOSFETs. Calculating the power dissipation in the driver for a
desired application is critical to ensuring safe operation.
Exceeding the maximum allowable power dissipation level will
push the IC beyond the maximum recommended operating
junction temperature of +125°C. When designing the
application, it is recommended that the following calculation be
MOSFET Selection and Considerations
The choice of MOSFETs depends on the current each MOSFET will
be required to conduct, the switching frequency, the capability of
the MOSFETs to dissipate heat, and the availability and nature of
heat sinking and air flow.
Typically, a MOSFET cannot tolerate even brief excursions beyond
their maximum drain to source voltage rating. The MOSFETs used
in the power stage of the converter should have a maximum V DS
rating that exceeds the sum of the upper voltage tolerance of the
input power source and the voltage spike that occurs when the
MOSFETs switch.
There are several power MOSFETs readily available that are
optimized for DC/DC converter applications. The preferred
high-side MOSFET emphasizes low gate charge so that the device
spends the least amount of time dissipating power in the linear
region. The preferred low-side MOSFET emphasizes low r DS(ON)
when fully saturated to minimize conduction loss.
For the low-side MOSFET, (LS), the power loss can be assumed to
be conductive only and is written as Equation 46:
P CON_LS ≈ I LOAD ? r DS ( ON ) _LS ? ( 1 – D )
performed to ensure safe operation at the desired frequency for
the selected MOSFETs. The power dissipated by the drivers is
2
(EQ. 46)
approximated as Equation 45:
P = F sw ( 1.5V U Q U + V L Q L ) + P L + P U
(EQ. 45)
For the high-side MOSFET, (HS), its conduction loss is written as
Equation 47:
P CON_HS = I LOAD ? r DS ( ON ) _HS ? D
Where:
2
(EQ. 47)
-
-
F sw is the switching frequency of the PWM signal
V U is the upper gate driver bias supply voltage
For the high-side MOSFET, its switching loss is written as
Equation 48:
- V L is the lower gate driver bias supply voltage
- Q U is the charge to be delivered by the upper driver into the
gate of the MOSFET and discrete capacitors
- Q L is the charge to be delivered by the lower driver into the
gate of the MOSFET and discrete capacitors
- P L is the quiescent power consumption of the lower driver
- P U is the quiescent power consumption of the upper driver
V IN ? I VALLEY ? t ON ? F SW V IN ? I PEAK ? t OFF ? F SW
2 2
P SW_HS = --------------------------------------------------------------- + ------------------------------------------------------------
(EQ. 48)
Where:
- I VALLEY is the difference of the DC component of the
inductor current minus 1/2 of the inductor ripple current
1000
900
800
Q U =100nC
Q L =200nC
Q U =50nC
Q L =100nC
Q U =50nC
Q L =50nC
- I PEAK is the sum of the DC component of the inductor
current plus 1/2 of the inductor ripple current
- t ON is the time required to drive the device into saturation
- t OFF is the time required to drive the device into cut-off
700
Layout Considerations
600
500
400
300
200
100
0
Q U =20nC
Q L =50nC
0 200 400 600 800 1k 1.2k 1.4k 1.6k 1.8k 2k
FREQUENCY (Hz)
FIGURE 21. POWER DISSIPATION vs FREQUENCY
24
As a general rule, power layers should be close together, either
on the top or bottom of the board, with the weak analog or logic
signal layers on the opposite side of the board. The ground-plane
layer should be adjacent to the signal layer to provide shielding.
The ground plane layer should have an island located under the
IC, the components connected to analog or logic signals. The
island should be connected to the rest of the ground plane layer
at one quiet point.
There are two sets of components in a DC/DC converter; the
power components and the small signal components. The power
components are the most critical because they switch large
amount of energy. The small signal components connect to
sensitive nodes or supply critical bypassing current and signal
coupling.
FN7933.1
March 2, 2012
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