参数资料
| 型号： | ISL95874IRUZ-T |
| 厂商： | Intersil |
| 文件页数： | 21/29页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 1PHASE GPU 16UTQFN |
| 标准包装： | 3,000 |
| 应用： | 控制器，GPU 内核电源 |
| 输入电压： | 3.3 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-UFQFN 裸露焊盘 |
| 供应商设备封装： | 16-UTQFN（2.6x1.8） |
| 包装： | 带卷 (TR) |
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ISL95874, ISL95875, ISL95876
Unlike the standard DC/DC buck regulator, the synchronous
rectifier can sink current from the output filter inductor during
The DC voltage difference between the OCSET pin and the VO pin,
which is given by Equation 34:
DCM, reducing the light-load efficiency with unnecessary
conduction loss as the low-side MOSFET sinks the inductor
current. The ISL95874, ISL95875, ISL95876 controllers avoid
V OCSET – V VO = V DCR – V ROCSET = I L ? DCR – I OCSET ? R OCSET
(EQ. 34)
I OCSET
V O
I L
_
R OCSET
+ V ROCSET
C SEN = -------------------------------------
(EQ. 36)
the DCM conduction loss by making the low-side MOSFET
emulate the current-blocking behavior of a diode. This
smart-diode operation called diode-emulation-mode (DEM) is
triggered when the negative inductor current produces a positive
voltage drop across the r DS(ON) of the low-side MOSFET for eight
consecutive PWM cycles while the LGATE pin is high. The
converter will exit DEM on the next PWM pulse after detecting a
negative voltage across the r DS(ON) of the low-side MOSFET.
It is characteristic of the R 4 architecture for the PWM switching
frequency to decrease while in DCM, increasing efficiency by
reducing unnecessary gate-driver switching losses. The extent of
the frequency reduction is proportional to the reduction of load
current. Upon entering DEM, the PWM frequency is forced to fall
approximately 30% by forcing a similar increase of the window
voltage V W . This measure is taken to prevent oscillating between
modes at the boundary between CCM and DCM. The 30%
increase of V W is removed upon exit of DEM, forcing the PWM
switching frequency to jump back to the nominal CCM value.
Overcurrent
The overcurrent protection (OCP) setpoint is programmed with
resistor R OCSET , which is connected across the OCSET and
PHASE pins. Resistor R O is connected between the VO pin and
the actual output voltage of the converter. During normal
operation, the VO pin is a high impedance path, therefore there is
no voltage drop across R O . The value of resistor R O should always
match the value of resistor R OCSET .
L
DCR
PHASE
+ V DCR
C SEN
C O
8.5μA _
OCSET
R O
VO
FIGURE 18. OVERCURRENT PROGRAMMING CIRCUIT
Figure 18 shows the overcurrent set circuit. The inductor consists
of inductance L and the DC resistance DCR. The inductor DC
current I L creates a voltage drop across DCR, which is given by
Equation 32:
The IC monitors the voltage of the OCSET pin and the VO pin.
When the voltage of the OCSET pin is higher than the voltage of
the VO pin for more than 10μs, an OCP fault latches the
converter off.
The value of R OCSET is calculated with Equation 35, written as:
I OC ? DCR (EQ. 35)
R OCSET = -------------------------
Where:
- R OCSET ( Ω ) is the resistor used to program the overcurrent
setpoint
- I OC is the output DC load current that will activate the OCP
fault detection circuit
- DCR is the inductor DC resistance
For example, if I OC is 20A and DCR is 4.5m Ω , the choice of
R OCSET is equal to 20A x 4.5m Ω /8.5μA = 10.5k Ω.
Resistor R OCSET and capacitor C SEN form an R-C network to
sense the inductor current. To sense the inductor current
correctly not only in DC operation, but also during dynamic
operation, the R-C network time constant R OCSET C SEN needs to
match the inductor time constant L/DCR. The value of C SEN is
then written as Equation 36:
L
R OCSET ? DCR
For example, if L is 1.5μH, DCR is 4.5m Ω , and R OCSET is 9k Ω, the
choice of C SEN = 1.5μH/(9k Ω x 4.5m Ω ) = 0.037μF .
When an OCP fault is declared, the converter will be latched off
and the PGOOD pin will be asserted low. The fault will remain
latched until the EN pin has been pulled below the falling EN
threshold voltage V ENTHF or if VCC has decayed below the falling
POR threshold voltage VVCC_THF .
Overvoltage
The OVP fault detection circuit triggers after the FB pin voltage is
above the rising overvoltage threshold V OVRTH for more than 2μs.
For example, if the converter is programmed to regulate 1.0V at
the FB pin, that voltage would have to rise above the typical
V OVRTH threshold of 116% for more than 2μs in order to trip the
OVP fault latch. In numerical terms, that would be
116% x 1.0V = 1.16V. When an OVP fault is declared, the
converter will be latched off and the PGOOD pin will be asserted
low. The fault will remain latched until the EN pin has been pulled
V DCR = I L ? DCR
(EQ. 32)
below the falling EN threshold voltage V ENTHF or if VCC has
decayed below the falling POR threshold voltage VVCC_THF .
The I OCSET current source sinks 8.5μA into the OCSET pin,
creating a DC voltage drop across the resistor R OCSET , which is
given by Equation 33:
V ROCSET = 8.5 μ A ? R OCSET
21
(EQ. 33)
FN7933.1
March 2, 2012
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