参数资料
| 型号： | ISL95874IRUZ-T |
| 厂商： | Intersil |
| 文件页数： | 25/29页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR PWM 1PHASE GPU 16UTQFN |
| 标准包装： | 3,000 |
| 应用： | 控制器，GPU 内核电源 |
| 输入电压： | 3.3 V ~ 25 V |
| 输出数： | 1 |
| 输出电压： | 0.5 V ~ 5 V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-UFQFN 裸露焊盘 |
| 供应商设备封装： | 16-UTQFN（2.6x1.8） |
| 包装： | 带卷 (TR) |
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ISL95874, ISL95875, ISL95876
VOUT
LOW-SIDE
INDUCTOR
MOSFETS
The power components should be placed first and these include
MOSFETs, input and output capacitors, and the inductor. Keeping
the distance between the power train and the control IC short
helps keep the gate drive traces short. These drive signals
include the LGATE, UGATE, PGND, PHASE and BOOT.
VIAS TO GND
GROUND OUTPUT
PLANE CAPACITORS
SCHOTTKY
DIODE
PHASE
NODE
HIGH-SIDE
MOSFETS INPUT
VIN CAPACITORS
FIGURE 22. TYPICAL POWER COMPONENT PLACEMENT
When placing MOSFETs, try to keep the source of the upper
MOSFETs and the drain of the lower MOSFETs as close as
thermally possible. See Figure 22. Input high frequency
capacitors should be placed close to the drain of the upper
MOSFETs and the source of the lower MOSFETs. Place the output
inductor and output capacitors between the MOSFETs and the
load. High frequency output decoupling capacitors (ceramic)
should be placed as close as possible to the decoupling target,
making use of the shortest connection paths to any internal
planes. Place the components in such a way that the area under
the IC has less noise traces with high dV/dt and di/dt, such as
gate signals and phase node signals.
VCC AND PVCC PINS
Place the decoupling capacitors as close as practical to the IC. In
particular, the PVCC decoupling capacitor should have a very
short and wide connection to the PGND pin. The VCC decoupling
capacitor should be referenced to GND pin.
25
EN, PGOOD, VID0, VID1, AND FSEL PINS
These are logic signals that are referenced to the GND pin. Treat
as a typical logic signal.
OCSET AND VO PINS
The current-sensing network consisting of R OCSET , R O , and C SEN
needs to be connected to the inductor pads for accurate
measurement of the DCR voltage drop. These components
however, should be located physically close to the OCSET and VO
pins with traces leading back to the inductor. It is critical that the
traces are shielded by the ground plane layer all the way to the
inductor pads. The procedure is the same for resistive current
sense.
FB, SREF, SET0, SET1, SET2, AND RTN PINS
The input impedance of these pins is high, making it critical to
place the components connected to these pins as close as
possible to the IC.
LGATE, PGND, UGATE, BOOT, AND PHASE PINS
The signals going through these traces are high dv/dt and high
di/dt, with high peak charging and discharging current. The
PGND pin can only flow current from the gate-source charge of
the low-side MOSFETs when LGATE goes low. Ideally, route the
trace from the LGATE pin in parallel with the trace from the PGND
pin, route the trace from the UGATE pin in parallel with the trace
from the PHASE pin. In order to have more accurate zero-crossing
detection of inductor current, it is recommended to connect the
PHASE pin to the drain of the low-side MOSFETs with Kelvin
connection. These pairs of traces should be short, wide, and
away from other traces with high input impedance; weak signal
traces should not be in proximity with these traces on any layer.
FN7933.1
March 2, 2012
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