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参数资料
| 型号： | ISPPAC-CLK5312S-01TN48C |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 11/56页 |
| 文件大小： | 0K |
| 描述： | IC CLOCK PROGRAM BUFFER 48TQFP |
| 标准包装： | 250 |
| 系列： | ispClock™ |
| 类型： | 时钟发生器，扇出配送，零延迟缓冲器 |
| PLL： | 带旁路 |
| 输入： | HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL |
| 输出： | eHSTL，HSTL，LVCMOS，LVTTL，SSTL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:12 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 267MHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-LQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
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Lattice Semiconductor
ispClock5300S Family Data Sheet
19
When the PLL is selected (PLL_BYPASS=LOW) and locked, the output frequency of each V divider (fk) may be cal-
culated as:
(1)
where
fk is the frequency of V divider k
fref is the input reference frequency
Vfbk is the setting of the V divider used to close the PLL feedback path
Vk is the output divider K
Note that because the feedback may be taken from any V divider, Vk and Vfbk may refer to the same divider.
Because the VCO has an operating frequency range spanning 160 MHz to 400 MHz, and the V dividers provide
division ratios from 1 to 32, the ispClock5300S can generate output signals ranging from 2.5 MHz to 267 MHz.
PLL_BYPASS Mode
The PLL_BYPASS mode is provided so that input reference signals can be coupled through to the outputs without
using the PLL functions. When PLL_BYPASS mode is enabled (PLL_BYPASS=HIGH), the reference clock is
routed directly to the inputs of the V dividers. The output frequency for a given V divider (fK) will be determined by
(2)
When PLL_BYPASS mode is enabled, features such as lock detect and skew generation are unavailable and the
output clock is inverted when VK=1.
Internal/External Feedback Support
The PLL feedback path can be sourced internally or externally through an output pin. When the internal feedback
path is selected, one can use all output pins for clock distribution. The programmable skew feature for the feedback
path is available in both feedback modes.
Reference and External Feedback Inputs
The ispClock5300S provides congurable, internally-terminated inputs for both clock reference and feedback sig-
nals.
The reference clock inputs pins can be interfaced with either one differential input (REFP, REFN) or two single-
ended (REFA, REFB) inputs with the active clock selection control through REFSEL pin. The following diagram
shows the possible reference clock congurations. Note: When the reference clock inputs are congured as differ-
ential input, the REFSEL pin should be grounded.
Table 2. REFSEL Operation for ispClock5300S Programmed as Single-Ended Clock Inputs
Supported input logic reference standards:
LVTTL (3.3V)
LVCMOS (1.8V, 2.5V, 3.3V)
SSTL2
SSTL3
HSTL
REFSEL
Selected
Input
0
REFA
1
REFB
=
fk
fref
Vfbk
Vk
=
fk
fREF
VK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ISPPACCLK5312S-01TN48C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ispPAC-CLK5312S-01TN48I | 功能描述:时钟驱动器及分配 ISP 0 Delay Unv Fan- Out Buf-Sngl End I RoHS:否 制造商:Micrel 乘法/除法因子:1:4 输出类型:Differential 最大输出频率:4.2 GHz 电源电压-最大: 电源电压-最小:5 V 最大工作温度:+ 85 C 封装 / 箱体:SOIC-8 封装:Reel |
| ISPPACCLK5312S-01TN48I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5312S-01TN64C | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
| ISPPACCLK5312S-01TN64I | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:In-System Programmable, Zero-Delay, Universal Fan-Out Buffer, Single-Ended |
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