ISPPAC-CLK5312S-01TN48C (Lattice) PDF资料下载 Datasheet(12/56 页)

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参数资料

型号：	ISPPAC-CLK5312S-01TN48C
厂商：	Lattice Semiconductor Corporation
文件页数：	12/56页
文件大小：	0K
描述：	IC CLOCK PROGRAM BUFFER 48TQFP
标准包装：	250
系列：	ispClock™
类型：	时钟发生器，扇出配送，零延迟缓冲器
PLL：	带旁路
输入：	HSTL，LVCMOS，LVDS，LVPECL，LVTTL，SSTL
输出：	eHSTL，HSTL，LVCMOS，LVTTL，SSTL
电路数：	1
比率 - 输入:输出：	2:12
差分 - 输入:输出：	是/无
频率 - 最大：	267MHz
除法器/乘法器：	是/无
电源电压：	3 V ~ 3.6 V
工作温度：	0°C ~ 70°C
安装类型：	表面贴装
封装/外壳：	48-LQFP
供应商设备封装：	48-TQFP（7x7）
包装：	托盘

Lattice Semiconductor

ispClock5300S Family Data Sheet

General Description

The ispClock5300S is an in-system-programmable zero delay universal fan-out buffer for use in clock distribution

applications. The ispClock5312S, the rst member of the ispClock5300S family, provides up to 12 single-ended

ultra low skew outputs. Each pair of outputs may be independently congured to support separate I/O standards

(LVTTL, LVCMOS -3.3V, 2.5V, 1.8, SSTL, HSTL) and output frequency. In addition, each output provides indepen-

dent programmable control of termination, slew-rate, and timing skew. All conguration information is stored on-

chip in non-volatile E

2CMOS memory.

The ispClock5300S devices provide extremely low propagation delay (zero-delay) from input to output using the

on-chip low jitter high-performance PLL. A set of three programmable 5-bit counters can be used to generate three

frequencies derived from the PLL clock. These counters are programmable in powers of 2 only (1, 2, 4, 8, 16, 32).

The clock output from any of the V-dividers can then be routed to any clock output pin through the output routing

matrix. The output routing matrix, in addition, also enables routing of reference clock inputs directly to any output.

The ispClock5300S device can be congured to operate in four modes: zero delay buffer mode, dual non-zero

delay buffer mode, non-zero delay buffer mode with output dividers, and combined zero-delay and non-zero delay

buffer mode.

The core functions of all members of the ispClock5300S family are identical. Table 1 summarizes the

ispClock5300S device family.

Table 1. ispClock5300S Family

Figure 1. ispClock5304S Functional Block Diagram

Device

Number of Programmable

Clock Inputs

Number of Programmable

Single-Ended Outputs

ispClock5320S