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参数资料
| 型号： | KIT33996EKEVB |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 14/24页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL 33996 16OUTPUT SW W/SPI |
| 标准包装： | 1 |
| 主要目的： | 电源管理，低端驱动器（内部 FET） |
| 嵌入式： | 否 |
| 已用 IC / 零件： | MC33996 |
| 主要属性： | 16 输出，5 ~ 27V，0.9 ~ 2.5A，SPI 接口，PWM 接口 |
| 次要属性： | 0.55 欧 RdsON，温度，过压，短路保护 |
| 已供物品： | 板，CD |
| 相关产品： | MC33996EK-ND - IC SWITCH 16OUTPUT W/SPI 32-SOIC MC33996EKR2-ND - IC SWITCH 16-OTPT W/SPI 32-SOIC |
LOGIC COMMANDS AND REGISTERS
INTRODUCTION
on output drain-to-source voltage (V DS ) > 2.7V. This feature
is designed to provide protection to loads that experience
more than expected currents and require fast shutdown. The
OR control to occur, the PWM Enable bit must be set to
logic [1].
33996 is designed to operate in both modes with full device
protection.
PWM ENABLE REGISTER
The PWM Enable register determines the outputs that are
PWM controlled. The first 8 bits of the 24 bit SPI message
On/Off Control Bit
PWM IN
AND/OR Control Bit
On/Off Control Bit
PWM Enable Bit
To Gate
Control
word are used to identify the PWM enable command, and the
remaining 16 bits are used to enable and disable the PWM of
the output drivers.
A logic [0] in the PWM Enable register will disable the
outputs as PWM. A logic [1] in the PWM Enable register will
set the specific output as a PWM. Power-ON Reset or the
RST pin or the RESET command will set the PWM Enable
register to logic [0].
AND/OR CONTROL REGISTER
The AND /OR Control register describes the condition by
which the PWM pin controls the output driver. A logic [0] in
the AND /OR Control register will AND the PWM input pin with
the ON /OFF Control register bit. Likewise, a logic [1] in the
AND /OR Control register will OR the PWM input pin with the
ON /OFF Control register bit (see Figure 12 ). For the AND /
On/Off control Bit
PWM IN
Figure 12. PWM Control Logic Diagram
SERIAL OUTPUT (SO) RESPONSE REGISTER
Fault reporting is accomplished through the SPI interface.
All logic [1s] received by the MCU via the SO pin indicate
fault. All logic [0s] received by the MCU via the SO pin
indicate no fault. All fault bits are cleared on the positive edge
of CS . SO bits 15 to 0 represent the fault status of outputs 15
to 0. SO bits 21 to 16 will always return logic [0]. Bit 22
provides over-voltage condition status and bit 23 is set when
any fault is present in the IC. The timing between two write
words must be greater than 450 μ s to allow adequate time to
sense and report the proper fault status.
RESET COMMAND
The RESET command turns all outputs OFF and sets the
following registers to a POR state (refer to Table 6 ).
? ON/OFF Control Register
? SFPD Control Register
? PWM Enable Register
? AND/OR Control Register
The Open Load Current Enable and the Global Shutdown
Registers are not affected by the RESET command.
33996
Analog Integrated Circuit Device Data
14
Freescale Semiconductor
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