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参数资料
型号： KSZ8842-16MBLI TR
厂商： Micrel Inc
文件页数： 106/141页
文件大小： 0K
描述： IC ETHERNET SW 2PORT 100LFBGA
标准包装： 1,000
控制器类型： 以太网开关控制器
接口： PCI
电源电压： 3.1 V ~ 3.5 V
工作温度： -40°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 100-LBGA
供应商设备封装： 100-LFBGA
包装： 带卷 (TR)
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
67
M9999-102207-1.9
Bank 17 TXQ Command Register (0x00): TXQCR
This register is programmed by the Host CPU to issue a transmit command to the TXQ. The present transmit frame in the
TXQ memory is queued for transmit.
Bit
Default Value
R/W
Description
15-1
-
RO
Reserved
0
0x0
RW
TXETF Enqueue TX Frame
When this bit is set as 1, the current TX frame prepared in the TX buffer is queued for
transmit.
Note: This bit is self-clearing after the frame is finished transmitting. The software
should wait for the bit to be cleared before setting up another new TX frame.
Bank 17 RXQ Command Register (0x02): RXQCR
This register is programmed by the Host CPU to issue release command to the RXQ. The current frame in the RXQ frame
buffer is read out by the host and the memory space is released.
Bit
Default Value
R/W
Description
15-1
-
RO
Reserved Do not write to this register.
0
0x0
RW
RXRRF Release RX Frame
When this bit is set as 1, the current RX frame buffer is released.
Note: This bit is self-clearing after the frame memory is released. The software should
wait for the bit to be cleared before processing new RX frames.
Bank 17 TX Frame Data Pointer Register (0x04): TXFDPR
The value of this register determines the address to be accessed within the TXQ frame buffer. When the AUTO increment
is set, It will automatically increment the pointer value on Write accesses to the data register.
The counter is incremented by one for every byte access, by two for every word access, and by four for every double
word access.
Bit
Default Value
R/W
Description
15
-
RO
Reserved
14
0x0
RW
TXFPAI TX Frame Data Pointer Auto Increment
When this bit is set, the TX Frame data pointer register increments automatically on
accesses to the data register. The increment is by one for every byte access, by two
for every word access, and by four for every doubleword access.
When this bit is reset, the TX frame data pointer is manually controlled by user to
access the TX frame location.
13-11
-
RO
Reserved
10-0
0x0
RW
TXFP TX Frame Pointer
TX Frame Pointer index to the Frame Data register for access.
This field reset to next available TX frame location when the TX Frame Data has been
enqueued through the TXQ command register.
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