参数资料
型号: KSZ8842-16MBLI TR
厂商: Micrel Inc
文件页数: 30/141页
文件大小: 0K
描述: IC ETHERNET SW 2PORT 100LFBGA
标准包装: 1,000
控制器类型: 以太网开关控制器
接口: PCI
电源电压: 3.1 V ~ 3.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-LBGA
供应商设备封装: 100-LFBGA
包装: 带卷 (TR)
Micrel, Inc.
KSZ8842-16/32 MQL/MVL/MVLI/MBL
October 2007
125
M9999-102207-1.9
Asynchronous Timing using Address Strobe (ADSN)
t2
t7
t5
t4
t3
t1
t6
t8
valid
Addr, AEN, BExN
ADSN
Read Data
RDN, WRN
Write Data
ARDY
(Read Cycle)
ARDY
(Write Cycle)
t9
t10
t11
Figure 18. Asynchronous Cycle – Using ADSN
Symbol
Parameter
Min
Typ
Max
Unit
t1
A1-A15, AEN, BExN[3:0] valid to RDN, WRN active
0
ns
t2
Read data valid to ARDY rising
0.8
ns
t3
Read data hold to RDN inactive
4
ns
t4
Write data setup to WRN inactive
4
ns
t5
Write data hold after WRN inactive
2
ns
t6
A1-A15, AEN, nBE[3:0] setup to ADSN rising
4
ns
t7
Read active to ARDY Low
8
ns
t8
A1-A15, AEN, BExN[3:0] hold after ADSN rising
2
ns
t9
Write inactive to ARDY Low
8
ns
ARDY low (wait time) in read cycle (Note1)
(It is 0ns to read bank select register and 40ns to
read QMU data register in turbo mode) (Note2)
0
40
ns
t10
ARDY low (wait time) in read cycle (Note1)
(It is 0ns to read bank select register and 80ns to
read QMU data register in normal mode)
0
80
ns
t11
ARDY low (wait time) in write cycle (Note1)
(It is 0ns to write bank select register)
(It is 36ns to write QMU data register)
0
50
ns
Note 1: When CPU finished current Read or Write operation, it can do next Read or Write operation even the
ARDY is low. During Read or Write operation if the ADRY is low, the CPU has to keep the RDN/WRN
low until the ARDY returns to high.
Note 2: In order to speed up the ARDY low time to 40 ns, user has to use the turbo software driver which is only
supported in the A6 device. Please refer to the “KSZ88xx Programmer's Guide” for detail.
Table 25. Asynchronous Cycle using ADSN Timing Parameters
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