
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101) 23
Channel Interface Port
These signals provide the physical connection to Channel Interface
devices, such as LSI Logic’s L64724 or L64768. This port supports both
parallel and serial connections.
CCLK
Channel Clock
Input
When CVALID is asserted HIGH, the L64118 latches
CDATA[7:0] on the rising edge of CCLK. In serial mode,
the L64118 uses only CDATA[0]. In serial mode, the
maximum clock rate is 60 MHz; in parallel mode, it is
13 MHz. The CCLK must toggle during reset to ensure
proper reset of the channel interface block.
CDATA[7:0]
Channel Data
Input
These signals deliver channel information to the L64118.
When CVALID is asserted, the chip latches the data on
every rising edge of CCLK. When the L64118 is in
parallel input mode, all CDATA[7:0] signals deliver data.
When the L64118 is in serial mode, only CDATA[0]
delivers data.
TTXREQ/GPIO12
oating
behaves as an input
TTXDATA
not asserted
TXD0/2
asserted
TXD1/ICE_TX
VVALID
not asserted
WRn
not asserted
1. A few cycles after reset (RESETn is driven HIGH), the L64118 initiates a
transaction on the EBus, changing some of the default values in this table.
Table 4
Default Values for L64118 Output and Bidirectional
Signals After Reset1 (Cont.)
Signal
Default Value
Notes
118bds Page 23 Wednesday, February 3, 1999 12:37 PM