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参数资料
| 型号： | L64118 |
| 厂商： | LSI CORP |
| 元件分类： | 消费家电 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA256 |
| 封装： | PLASTIC, BGA-256 |
| 文件页数： | 32/68页 |
| 文件大小： | 877K |
| 代理商： | L64118 |
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38
L64118 MPEG-2 Transport Controller with Embedded MIPS CPU (TR4101)
IEEE1284 Parallel Port and Auxiliary Port
These signals provide a parallel connection between the L64118 and an
external peripheral device. The port complies to IEEE1284 standards
and supports several modes. The 1284 mode is enabled when the
AUX_SEL bit is reset (System Mode register, bit 4).
This port also serves as an auxiliary port for receiving and transmitting
transport bitstreams from various points in the on-chip demultiplexer
pipeline. The Aux mode is enabled when the AUX_SEL bit is set (System
Mode register, bit 4).
The following list shows each pin’s functionality as an IEEE1284 port and
Aux port signal. Some of these pins also can serve as general-purpose
I/O pins.
ACKn/AUXNM
1284 - Acknowledge
Output
When the L64118 asserts this signal, valid data is latched
in the L64118 IEEE1284 input register. By default, this
signal is not asserted after reset.
Aux - Aux No Match
Output
In Aux mode, this signal functions as AUXNM to indicate
that the data being sent through the auxiliary port is for
a transport packet that failed PID ltering.
AUTOFDn/AUXV
1284 - Autofeed
Input
In 1284 mode, this pin functions as the Autofeed input.
Aux - Data Valid
Bidirectional
In Aux mode, this pin functions as AUXV, which is used
as a qualier indicating that the data presented on the
auxiliary data bus is valid.
GPIO14
Bidirectional
This signal can serve as a general-purpose I/O signal
(GPIO14) by setting bit 3 in the General-Purpose Mode
register.
118bds Page 38 Wednesday, February 3, 1999 12:37 PM
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